View LH75401N0Q100C0_4844581.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

LH75401/LH75411
Preliminary data sheet
DESCRIPTION
The NXP BlueStreak LH75401/LH75411 family consists of two low-cost 16/32-bit System-on-Chip (SoC) devices. * LH75401 -- contains the superset of features. * LH75411 -- similar to LH75401, without CAN 2.0B.
System-on-Chip
* JTAG Debug Interface and Boundary Scan * Single 3.3 V Supply * 5 V Tolerant Digital I/O - XTALIN and XTAL32IN inputs are 1.8 V 10 % * 144-pin LQFP Package * -40C to +85C Operating Temperature
COMMON FEATURES
* Highly Integrated System-on-Chip * ARM7TDMI-STM Core * High Performance (84 MHz CPU Speed) - Internal PLL Driven or External Clock Driven - Crystal Oscillator/Internal PLL Can Operate with Input Frequency Range of 14 MHz to 20 MHz * 32 kB On-chip SRAM - 16 kB Tightly Coupled Memory (TCM) SRAM - 16 kB Internal SRAM * Clock and Power Management - Low Power Modes: Standby, Sleep, Stop * Eight Channel, 10-bit Analog-to-Digital Converter * Integrated Touch Screen Controller * Serial interfaces - Two 16C550-type UARTs supporting baud rates up to 921,600 baud (requires crystal frequency of 14.756 MHz). - One 82510-type UART supporting baud rates up to 3,225,600 baud (requires a system clock of 70 MHz). * Synchronous Serial Port - Motorola SPITM - National Semiconductor MicrowireTM - Texas Instruments SSI * Real-Time Clock (RTC) * Three Counter/Timers - Capture/Compare/PWM Compatibility - Watchdog Timer (WDT) * Low-Voltage Detector
Unique Features of the LH75401
* Color and Grayscale Liquid Crystal Display (LCD) Controller - 12-bit (4,096) Direct Mode Color, up to VGA - 8-bit (256) Direct or Palettized Color, up to SVGA - 4-bit (16) Direct Mode Color/Grayscale, up to XGA - 12-bit Video Bus - Supports STN, TFT, HR-TFT, and AD-TFT Displays. * CAN Controller that supports CAN version 2.0B.
Unique Features of the LH75411
* Color and Grayscale LCD Controller (LCDC) - 12-bit (4,096) Direct Mode Color, up to VGA - 8-bit (256) Direct or Palettized Color, up to SVGA - 4-bit (16) Direct Mode Color/Grayscale, up to XGA - 12-bit Video Bus - Supports STN, TFT, HR-TFT, and AD-TFT Displays.
Preliminary data sheet
1
LH75401/LH75411
NXP Semiconductors
System-on-Chip
ORDERING INFORMATION
Table 1. Ordering information Package Type number Name LH75401N0Q100C0 LH75411N0Q100C0 LQFP144 LQFP144 Description plastic low profile quad flat package; 144 leads; body 20 x 20 x 1.4 mm plastic low profile quad flat package; 144 leads; body 20 x 20 x 1.4 mm SOT486-1 SOT486-1 Version
2
Rev. 01 -- 16 July 2007
Preliminary data sheet
System-on-Chip
NXP Semiconductors
LH75401/LH75411
LH75401 BLOCK DIAGRAM
LH75401
14 to 20 MHz 32.768 kHz
OSCILLATOR, PLL, POWER MANAGEMENT, and RESET CONTROL
REAL TIME CLOCK
INTERNAL 16KB SRAM
76-BIT GENERAL PURPOSE I/O
ARM7TDMI-S
AHB INTERFACE VECTORED INTERRUPT CONTROLLER
I/O CONFIGURATION
TCM 16KB SRAM
SYNCHRONOUS SERIAL PORT 4 CHANNEL DMA CONTROLLER
STATIC MEMORY CONTROLLER
TIMER (3)
ADVANCED PERIPHERAL BUS BRIDGE
WATCHDOG TIMER
BROWNOUT DETECTOR
COLOR LCD CONTROLLER
CAN 2.0B
LINEAR REGULATOR
ADVANCED LCD INTERFACE
UART (3)
8 CHANNEL 10-BIT ADC TOUCH PANEL INTERFACE ADVANCED HIGH PERFORMANCE BUS (AHB) ADVANCED PERPHERAL BUS (APB)
LH75401-1
Figure 1. LH75401 Block Diagram
Preliminary data sheet
Rev. 01 -- 16 July 2007
3
LH75401/LH75411
NXP Semiconductors
System-on-Chip
LH75411 BLOCK DIAGRAM
LH75411
14 to 20 MHz 32.768 kHz
OSCILLATOR, PLL, POWER MANAGEMENT, and RESET CONTROL
REAL TIME CLOCK
INTERNAL 16KB SRAM
76-BIT GENERAL PURPOSE I/O
ARM 7TDMI-S
AHB INTERFACE VECTORED INTERRUPT CONTROLLER
I/O CONFIGURATION
TCM 16KB SRAM
SYNCHRONOUS SERIAL PORT 4 CHANNEL DMA CONTROLLER
STATIC MEMORY CONTROLLER
TIMER (3)
ADVANCED PERIPHERAL BUS BRIDGE
WATCHDOG TIMER
BROWNOUT DETECTOR
COLOR LCD CONTROLLER
UART (3)
LINEAR REGULATOR ADVANCED HIGH PERFORMANCE BUS (AHB)
ADVANCED LCD INTERFACE
8 CHANNEL 10-BIT ADC TOUCH PANEL INTERFACE
ADVANCED PERPHERAL BUS (APB)
LH75411-1
Figure 2. LH75411 Block Diagram
4
Rev. 01 -- 16 July 2007
Preliminary data sheet
System-on-Chip
NXP Semiconductors
LH75401/LH75411
PIN CONFIGURATION
144
1
109 108
LH75401/ LH75411
36 37 72
73
002aad207
Figure 3. LH75401/LH75411 pin configuration
Preliminary data sheet
Rev. 01 -- 16 July 2007
5
LH75401/LH75411
NXP Semiconductors
System-on-Chip
LH75401 Numerical Pin Listing
Table 2. LH75401 Numerical Pin List
PIN NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 FUNCTION AT RESET PA7 PA6 VDD PA5 PA4 PA3 PA2 VSS PA1 PA0 VDDC D7 D6 VSSC D5 D4 VDD D3 D2 D1 D0 nWE nOE PB5 PB4 VSS PB3 PB2 PB1 PB0 nCS0 PC7 PC6 VDD PC5 PC4 PC3 PC2 A21 A20 A19 A18 A23 A22 Power nBLE0 nCS3 nCS2 nCS1 nWAIT nBLE1 Ground D9 D8 D13 D12 D11 D10 FUNCTION 2 D15 D14 FUNCTION FUNCTION OUTPUT 3 TYPE DRIVE I/O I/O Power I/O I/O I/O I/O Ground I/O I/O Power I/O I/O Ground I/O I/O Power I/O I/O I/O I/O 8 mA 8 mA None 8 mA 8 mA 8 mA 8 mA None 8 mA 8 mA None 8 mA 8 mA None 8 mA 8 mA None 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA None 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA None 8 mA 8 mA 8 mA 8 mA Bidirectional Bidirectional Bidirectional Bidirectional
Pull-down Pull-down Pull-down Pull-down
BUFFER TYPE Bidirectional Bidirectional
BEHAVIOR DURING RESET Pull-up Pull-up
NOTES 1 1
Bidirectional Bidirectional Bidirectional Bidirectional
Pull-up Pull-up Pull-up Pull-up
1 1 1 1
Bidirectional Bidirectional
Pull-up Pull-up
1 1
Bidirectional Bidirectional
Pull-up Pull-up
Bidirectional Bidirectional
Pull-up Pull-up
Bidirectional Bidirectional Bidirectional Bidirectional Output Output Bidirectional Bidirectional
Pull-up Pull-up Pull-up Pull-up HIGH HIGH Pull-up Pull-up 3 3 1, 3 1, 3
Bidirectional Bidirectional Bidirectional Bidirectional Output Bidirectional Bidirectional
Pull-up Pull-up Pull-up Pull-up Pull-up
Pull-down Pull-down
1, 3 1, 3 1, 3 1, 3 3 1 1 1 1 1 1
6
Rev. 01 -- 16 July 2007
Preliminary data sheet
System-on-Chip
NXP Semiconductors
LH75401/LH75411
Table 2. LH75401 Numerical Pin List (Cont'd)
PIN NO. 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 FUNCTION AT RESET PC1 PC0 VSS VDD A15 A14 A13 A12 A11 VSS A10 A9 A8 A7 A6 VDD A5 A4 A3 A2 VSS A1 A0 nRESETIN TEST2 TEST1 TMS RTCK TCK TDI TDO LINREGEN nRESETOUT PD6 PD5 PD4 VDDC PD3 PD2 PD1 PD0 VSSC INT3 INT2 INT1 INT0 Ground UARTTX1 INT6 INT5 INT4 DREQ DACK UARTRX1 Power Ground Power Ground FUNCTION 2 A17 A16 Ground Power FUNCTION FUNCTION OUTPUT 3 TYPE DRIVE 8 mA 8 mA None None 8 mA 8 mA 8 mA 8 mA 8 mA None 8 mA 8 mA 8 mA 8 mA 8 mA None 8 mA 8 mA 8 mA 8 mA None 8 mA 8 mA None None None None 8 mA None None 4 mA None 8 mA 6 mA 6 mA 8 mA None 8 mA 2 mA 6 mA 2 mA None Bidirectional Bidirectional Bidirectional Bidirectional Pull-up Pull-up 1 1 1, 2 1 Output Output Input Input Input Input Output Input Input Output Input Output Bidirectional Bidirectional Bidirectional Pull-up Pull-down 5 3 1 1, 2 1 Pull-up 2 LOW LOW Pull-up Pull-up Pull-up Pull-up 2, 3 2 2 2 Output Output Output Output LOW LOW LOW LOW Output Output Output Output Output LOW LOW LOW LOW LOW Output Output Output Output Output LOW LOW LOW LOW LOW BUFFER TYPE Bidirectional Bidirectional BEHAVIOR DURING RESET
Pull-down Pull-down
NOTES 1 1
Preliminary data sheet
Rev. 01 -- 16 July 2007
7
LH75401/LH75411
NXP Semiconductors
System-on-Chip
Table 2. LH75401 Numerical Pin List (Cont'd)
PIN NO. 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 FUNCTION AT RESET nPOR XTAL32IN XTAL32OUT VSSA_PLL VDDA_PLL XTALIN XTALOUT VSSA_ADC AN3 (LR/Y-) AN4 (Wiper) AN9 AN2 (LL/Y+) AN8 AN1 (UR/X-) AN6 AN0 (UL/X+) VDDA_ADC VDD PE7 PE6 PE5 PE4 PE3 PE2 PE1 VSS PE0 PF6 PF5 PF4 PF3 VDD PF2 PF1 PF0 PG7 PG6 PG5 VSS PG4 PG3 PG2 LCDVEEEN LCDVDDEN LCDDSPLEN LCDREV LCDMOD CTCAP0E CTCAP0D CTCAP0C CTCAP0B CTCAP0A CTCLK Ground CTCMP0B CTCMP0A UARTRX2 CTCAP2B CTCAP2A CTCAP1B CTCAP1A CTCMP2B CTCMP2A CACMP1B CTCMP1A Power SSPFRM SSPCLK SSPRX SSPTX CANTX CANRX UARTTX2 Ground UARTTX0 UARTRX0 PJ7 PJ6 PJ5 PJ4 PJ3 PJ2 PJ1 PJ0 Power Power Ground Ground Power FUNCTION 2 FUNCTION FUNCTION OUTPUT 3 TYPE DRIVE None None None None None None None None None None None None None None None None None None 4 mA 4 mA 4 mA 4 mA 8 mA 2 mA 4 mA None 4 mA 4 mA 4 mA 4 mA 4 mA None 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA None 8 mA 8 mA 8 mA Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional 2 2 2 Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional 2 Pull-up 1 2 Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Pull-up Pull-down Pull-up Pull-down Pull-up Pull-up Pull-up 1 1 1 1 1 1 1 Input Input Input Input Input Input Input Input Input Output 4 BUFFER TYPE Input Input Output BEHAVIOR DURING RESET Pull-up NOTES 2, 3 4
8
Rev. 01 -- 16 July 2007
Preliminary data sheet
System-on-Chip
NXP Semiconductors
LH75401/LH75411
Table 2. LH75401 Numerical Pin List (Cont'd)
PIN NO. 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 NOTES:
1. 2. 3. 4. 5. Signal is selectable as pull-up, pull-down, or no pull-up/pull-down via the I/O Configuration peripheral. CMOS Schmitt trigger input. Signals preceded with `n' are active LOW. Crystal Oscillator Inputs should be driven to 1.8 V 10 % (MAX.) LINREGEN activation requires a 0 pull-up to VDD.
FUNCTION AT RESET PG1 PG0 PH7 VDD VSS PH6 PH5 PH4 PH3 PH2 PH1 VDD PH0 PI7 PI6 PI5 PI4 VSS PI3 PI2 PI1 PI0
FUNCTION 2 LCDCLS LCDPS LCDDCLK
FUNCTION FUNCTION OUTPUT 3 TYPE DRIVE 8 mA 8 mA 8 mA Power Ground None None 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA Power None 8 mA 8 mA 8 mA 8 mA 8 mA Ground None 8 mA 8 mA 8 mA 8 mA
BUFFER TYPE Bidirectional Bidirectional Bidirectional
BEHAVIOR DURING RESET
NOTES
LCDLP LCDFP LCDEN LCDVD11 LCDVD10 LCDVD9 LCDVD8 LCDVD7 LCDVD6 LCDVD5 LCDVD4 LCDVD3 LCDVD2 LCDVD1 LCDVD0
LCDHRLP LCDSPS LCDSPL
Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional
Preliminary data sheet
Rev. 01 -- 16 July 2007
9
LH75401/LH75411
NXP Semiconductors
System-on-Chip
LH75401 Signal Descriptions
Table 3. LH75401 Signal Descriptions
PIN NO. 1 2 4 5 6 7 9 10 12 13 15 16 18 19 20 21 22 23 24 25 27 28 29 30 31 32 33 35 36 37 38 39 40 43 44 45 46 47 49 50 51 52 53 55 56 57 58 60 61 72 73 SIGNAL NAME TYPE DESCRIPTION MEMORY INTERFACE (MI) NOTES
D[15:0]
Input/Output Data Input/Output Signals
1
nWE nOE nWAIT nBLE1 nBLE0 nCS3 nCS2 nCS1 nCS0
Output Output Input Output Output Output Output Output Output
Static Memory Controller Write Enable Static Memory Controller Output Enable Static Memory Controller External Wait Control Static Memory Controller Byte Lane Strobe Static Memory Controller Byte Lane Strobe Static Memory Controller Chip Select Static Memory Controller Chip Select Static Memory Controller Chip Select Static Memory Controller Chip Select
2 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 2
A[23:0]
Output
Address Signals
1
DMA CONTROLLER (DMAC) DREQ DACK Input Output DMA Request DMA Acknowledge 1 1
10
Rev. 01 -- 16 July 2007
Preliminary data sheet
System-on-Chip
NXP Semiconductors
LH75401/LH75411
Table 3. LH75401 Signal Descriptions (Cont'd)
PIN NO. 120 120 121 122 122 123 124 125 128 128 129 129 130 130 131 132 133 135 136 137 138 139 141 142 143 144 99 100 101 102 103 104 74 76 105 107 103 104 SIGNAL NAME LCDMOD LCDVEEEN LCDVDDEN LCDDSPLEN LCDREV LCDCLS LCDPS LCDDCLK LCDLP LCDHRLP LCDFP LCDSPS LCDEN LCDSPL TYPE Output Output Output Output Output Output Output Output Output Output Output Output Output Output DESCRIPTION COLOR LCD CONTROLLER (CLCDC) Signal Used by the Row Driver (AD-TFT, HR-TFT only) Analog Supply Enable (AC Bias SIgnal) Digital Supply Enable LCD Panel Power Enable Reverse Signal (AD-TFT, HR-TFT only) Clock to the Row Drivers (AD-TFT, HR-TFT only) Power Save (AD-TFT, HR-TFT only) LCD Panel Clock Line Synchronization Pulse (STN), Horizontal Synchronization Pulse (TFT) Latch Pulse (AD-TFT, HR-TFT only) Frame Pulse (STN), Vertical Synchronization Pulse (TFT) Row Driver Counter Reset Signal (AD-TFT, HR-TFT only) LCD Data Enable Start Pulse Left (AD-TFT, HR-TFT only) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 NOTES
LCDVD[11:0]
Output
LCD Panel Data bus
1
SYNCHRONOUS SERIAL PORT (SSP) SSPFRM SSPCLK SSPRX SSPTX UARTTX0 UARTRX0 UARTRX1 UARTTX1 UARTTX2 UARTRX2 CANTX CANRX Output Output Input Output Output Input Input Output Output Input Output Input SSP Serial Frame SSP Clock SSP RXD SSP TXD UART0 (U0) UART0 Transmitted Serial Data Output UART0 Received Serial Data Input UART1 (U1) UART1 Received Serial Data Input UART1 Transmitted Serial Data Output UART2 (U2) UART2 Transmitted Serial Data Output UART2 Received Serial Data Input CONTROLLER AREA NETWORK (CAN) CAN Transmitted Serial Data Output CAN Received Serial Data Input 1 1 1 1 1 1 1 1 1 1 1 1
Preliminary data sheet
Rev. 01 -- 16 July 2007
11
LH75401/LH75411
NXP Semiconductors
System-on-Chip
Table 3. LH75401 Signal Descriptions (Cont'd)
PIN NO. 89 90 91 92 93 94 95 96 117 116 115 114 113 117 116 118 111 110 111 110 118 109 108 109 108 118 1 2 4 5 6 7 9 10 24 25 27 28 29 30 32 33 35 36 37 38 39 40 SIGNAL NAME AN3 (LR/Y-) AN4 (Wiper) AN9 AN2 (LL/Y+) AN8 AN1 (UR/X-) AN6 AN0 (UL/X+) TYPE DESCRIPTION ANALOG-TO-DIGITAL CONVERTER (ADC) NOTES
Input
ADC Inputs
1
TIMER 0
CTCAP0[A:E]
Input
Timer 0 Capture Inputs
1
CTCMP0[A:B] CTCLK
Output Input
Timer 0 Compare Outputs Common External Clock TIMER 1
1 1
CTCAP1[A:B] CTCMP1[A:B] CTCLK
Input Output Input
Timer 1 Capture Inputs Timer 1 Compare Outputs Common External Clock TIMER 2
1 1 1
CTCAP2[A:B] CTCMP2[A:B] CTCLK PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PB5 PB4 PB3 PB2 PB1 PB0 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0
Input Input Input
Timer 2 Capture Inputs Timer 2 Compare Outputs Common External Clock GENERAL PURPOSE INPUT/OUTPUT (GPIO)
1 1 1
Input/Output General Purpose I/O Signals - Port A
1
Input/Output General Purpose I/O Signals - Port B
1
Input/Output General Purpose I/O Signals - Port C
1
12
Rev. 01 -- 16 July 2007
Preliminary data sheet
System-on-Chip
NXP Semiconductors
LH75401/LH75411
Table 3. LH75401 Signal Descriptions (Cont'd)
PIN NO. 72 73 74 76 77 78 79 89 90 91 92 93 94 95 96 99 100 101 102 103 104 105 107 108 109 110 111 113 114 115 116 117 118 120 121 122 123 124 125 128 129 130 131 132 133 135 136 137 138 139 141 142 143 144 62 71 72 SIGNAL NAME PD6 PD5 PD4 PD3 PD2 PD1 PD0 PJ7 PJ6 PJ5 PJ4 PJ3 PJ2 PJ1 PJ0 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 PF6 PF5 PF4 PF3 PF2 PF1 PF0 PG7 PG6 PG5 PG4 PG3 PG2 PG1 PG0 PH7 PH6 PH5 PH4 PH3 PH2 PH1 PH0 PI7 PI6 PI5 PI4 PI3 PI2 PI1 PI0 nRESETIN nRESETOUT INT6 TYPE DESCRIPTION NOTES
Input/Output General Purpose I/O Signals - Port D
1
Input
General Purpose I/O Signals - Port J
1
Input/Output General Purpose I/O Signals - Port E
1
Input/Output General Purpose I/O Signals - Port F
1
Input/Output General Purpose I/O Signals - Port G
1
Input/Output General Purpose I/O Signals - Port H
1
Input/Output General Purpose I/O Signals - Port I
1
RESET, CLOCK, AND POWER CONTROLLER (RCPC) Input Output Input User Reset Input System Reset Output External Interrupt Input 6 2 2 1
Preliminary data sheet
Rev. 01 -- 16 July 2007
13
LH75401/LH75411
NXP Semiconductors
System-on-Chip
Table 3. LH75401 Signal Descriptions (Cont'd)
PIN NO. 73 74 76 77 78 79 81 82 83 86 87 63 64 65 66 67 68 69 3 17 34 42 54 98 112 126 134 8 26 41 48 59 106 119 127 140 11 75 14 80 70 84 85 88 97 SIGNAL NAME INT5 INT4 INT3 INT2 INT1 INT0 nPOR XTAL32IN XTAL32OUT XTALIN XTALOUT TEST2 TEST1 TMS RTCK TCK TDI TDO TYPE Input Input Input Input Input Input Input Input Output Input Output Input Input Input Output Input Input Output External Interrupt Input 5 External Interrupt Input 4 External Interrupt Input 3 External Interrupt Input 2 External Interrupt Input 1 External Interrupt Input 0 Power-on Reset Input 32.768 kHz Crystal Clock Input 32.768 kHz Crystal Clock Output Crystal Clock Input Crystal Clock Output TEST INTERFACE Test Mode Pin 2 Test Mode Pin 1 JTAG Test Mode Select Input Returned JTAG Test Clock Output JTAG Test Clock Input JTAG Test Serial Data Input JTAG Test Data Serial Output POWER AND GROUND (GND) DESCRIPTION NOTES 1 1 1 1 1 1 2
VDD
Power
I/O Ring VDD
VSS
Power
I/O Ring VSS
VDDC VSSC LINREGEN VSSA_PLL VDDA_PLL VSSA_ADC VDDA_ADC
Power Power Input Power Power Power Power
Core VDD supply (Output if Linear Regulator Enabled, Otherwise Input) Core VSS Linear Regulator Enable PLL Analog VSS PLL Analog VDD Supply A-to-D converter Analog VSS A-to-D converter Analog VDD Supply
NOTES: 1. These pin numbers have multiplexed functions. 2. Signals preceded with `n' are active LOW.
14
Rev. 01 -- 16 July 2007
Preliminary data sheet
System-on-Chip
NXP Semiconductors
LH75401/LH75411
LH75411 Numerical Pin Listing
Table 4. LH75411 Numerical Pin List
PIN NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 FUNCTION AT RESET PA7 PA6 VDD PA5 PA4 PA3 PA2 VSS PA1 PA0 VDDC D7 D6 VSSC D5 D4 VDD D3 D2 D1 D0 nWE nOE PB5 PB4 VSS PB3 PB2 PB1 PB0 nCS0 PC7 PC6 VDD PC5 PC4 PC3 PC2 PC1 PC0 VSS A21 A20 A19 A18 A17 A16 Ground A23 A22 Power nBLE0 nCS3 nCS2 nCS1 nWAIT nBLE1 Ground D9 D8 D13 D12 D11 D10 FUNCTION 2 D15 D14 FUNCTION FUNCTION OUTPUT 3 TYPE DRIVE I/O I/O Power I/O I/O I/O I/O Ground I/O I/O Power I/O I/O Ground I/O I/O Power I/O I/O I/O I/O 8 mA 8 mA None 8 mA 8 mA 8 mA 8 mA None 8 mA 8 mA None 8 mA 8 mA None 8 mA 8 mA None 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA None 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA None 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA None Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional
Pull-down Pull-down Pull-down Pull-down Pull-down Pull-down
BUFFER TYPE Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Output Output Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Output Bidirectional Bidirectional
BEHAVIOR DURING RESET Pull-up Pull-up Pull-up Pull-up Pull-up Pull-up Pull-up Pull-up Pull-up Pull-up Pull-up Pull-up Pull-up Pull-up Pull-up Pull-up HIGH HIGH Pull-up Pull-up Pull-up Pull-up Pull-up Pull-up Pull-up
Pull-down Pull-down
NOTES 1 1 1 1 1 1 1 1
3 3 1, 3 1, 3 1, 3 1, 3 1, 3 1, 3 3 1 1 1 1 1 1 1 1
Preliminary data sheet
Rev. 01 -- 16 July 2007
15
LH75401/LH75411
NXP Semiconductors
System-on-Chip
Table 4. LH75411 Numerical Pin List (Cont'd)
PIN NO. 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 FUNCTION AT RESET VDD A15 A14 A13 A12 A11 VSS A10 A9 A8 A7 A6 VDD A5 A4 A3 A2 VSS A1 A0 nRESETIN TEST2 TEST1 TMS RTCK TCK TDI TDO LINREGEN nRESETOUT PD6 PD5 PD4 VDDC PD3 PD2 PD1 PD0 VSSC nPOR XTAL32IN XTAL32OUT INT3 INT2 INT1 INT0 Ground UARTTX1 INT6 INT5 INT4 DREQ DACK UARTRX1 Power Ground Power Ground FUNCTION 2 FUNCTION FUNCTION OUTPUT 3 TYPE DRIVE Power None 8 mA 8 mA 8 mA 8 mA 8 mA None 8 mA 8 mA 8 mA 8 mA 8 mA None 8 mA 8 mA 8 mA 8 mA None 8 mA 8 mA None None None None 8 mA None None 4 mA None 8 mA 6 mA 6 mA 8 mA None 8 mA 2 mA 6 mA 2 mA None None None None Input Input Output Pull-up 2, 3 4 Bidirectional Bidirectional Bidirectional Bidirectional Pull-up Pull-up 1 1 1, 2 1 Output Output Input Input Input Input Output Input Input Output Input Output Bidirectional Bidirectional Bidirectional Pull-up Pull-down 5 3 1 1, 2 1 Pull-up 2 LOW LOW Pull-up Pull-up Pull-up Pull-up 2, 3 2 2 2 Output Output Output Output LOW LOW LOW LOW Output Output Output Output Output LOW LOW LOW LOW LOW Output Output Output Output Output LOW LOW LOW LOW LOW BUFFER TYPE BEHAVIOR DURING RESET NOTES
16
Rev. 01 -- 16 July 2007
Preliminary data sheet
System-on-Chip
NXP Semiconductors
LH75401/LH75411
Table 4. LH75411 Numerical Pin List (Cont'd)
PIN NO. 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 FUNCTION AT RESET VSSA_PLL VDDA_PLL XTALIN XTALOUT VSSA_ADC AN3 (LR/Y-) AN4 (Wiper) AN9 AN2 (LL/Y+) AN8 AN1 (UR/X-) AN6 AN0 (UL/X+) VDDA_ADC VDD PE7 PE6 PE5 PE4 PE3 PE2 PE1 VSS PE0 PF6 PF5 PF4 PF3 VDD PF2 PF1 PF0 PG7 PG6 PG5 VSS PG4 PG3 PG2 PG1 PG0 PH7 LCDVEEEN LCDVDDEN LCDDSPLEN LCDCLS LCDPS LCDDCLK LCDREV LCDMOD CTCAP0E CTCAP0D CTCAP0C CTCAP0B CTCAP0A CTCLK Ground CTCMP0B CTCMP0A UARTRX2 CTCAP2B CTCAP2A CTCAP1B CTCAP1A CTCMP2B CTCMP2A CACMP1B CTCMP1A Power SSPFRM SSPCLK SSPRX SSPTX UARTTX0 UARTRX0 UARTTX2 Ground PJ7 PJ6 PJ5 PJ4 PJ3 PJ2 PJ1 PJ0 Power Power Ground FUNCTION 2 FUNCTION FUNCTION OUTPUT 3 TYPE DRIVE Ground Power None None None None None None None None None None None None None None None 4 mA 4 mA 4 mA 4 mA 8 mA 2 mA 4 mA None 4 mA 4 mA 4 mA 4 mA 4 mA None 4 mA 4 mA 4 mA 4 mA 4 mA 4 mA None 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional 2 2 2 Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional 2 Pull-up 1 2 Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Pull-up Pull-down Pull-up Pull-down Pull-up Pull-up Pull-up 1 1 1 1 1 1 1 Input Input Input Input Input Input Input Input Input Output 4 BUFFER TYPE BEHAVIOR DURING RESET NOTES
Preliminary data sheet
Rev. 01 -- 16 July 2007
17
LH75401/LH75411
NXP Semiconductors
System-on-Chip
Table 4. LH75411 Numerical Pin List (Cont'd)
PIN NO. 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 NOTES:
1. 2. 3. 4. 5. Signal is selectable as pull-up, pull-down, or no pull-up/pull-down via the I/O Configuration peripheral. CMOS Schmitt trigger input. Signals preceded with `n' are active LOW. Crystal Oscillator Inputs should be driven to 1.8 V 10 % (MAX.) LINREGEN activation requires a 0 pull-up to VDD.
FUNCTION AT RESET VDD VSS PH6 PH5 PH4 PH3 PH2 PH1 VDD PH0 PI7 PI6 PI5 PI4 VSS PI3 PI2 PI1 PI0
FUNCTION 2
FUNCTION FUNCTION OUTPUT 3 TYPE DRIVE Power Ground None None 8 mA 8 mA 8 mA 8 mA 8 mA 8 mA Power None 8 mA 8 mA 8 mA 8 mA 8 mA Ground None 8 mA 8 mA 8 mA 8 mA
BUFFER TYPE
BEHAVIOR DURING RESET
NOTES
LCDLP LCDFP LCDEN LCDVD11 LCDVD10 LCDVD9 LCDVD8 LCDVD7 LCDVD6 LCDVD5 LCDVD4 LCDVD3 LCDVD2 LCDVD1 LCDVD0
LCDHRLP LCDSPS LCDSPL
Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional
18
Rev. 01 -- 16 July 2007
Preliminary data sheet
System-on-Chip
NXP Semiconductors
LH75401/LH75411
LH75411 Signal Descriptions
Table 5. LH75411 Signal Descriptions
PIN NO. 1 2 4 5 6 7 9 10 12 13 15 16 18 19 20 21 22 23 24 25 27 28 29 30 31 32 33 35 36 37 38 39 40 43 44 45 46 47 49 50 51 52 53 55 56 57 58 60 61 72 73 SIGNAL NAME TYPE DESCRIPTION MEMORY INTERFACE (MI) NOTES
D[15:0]
Input/Output Data Input/Output Signals
1
nWE nOE nWAIT nBLE1 nBLE0 nCS3 nCS2 nCS1 nCS0
Output Output Input Output Output Output Output Output Output
Static Memory Controller Write Enable Static Memory Controller Output Enable Static Memory Controller External Wait Control Static Memory Controller Byte Lane Strobe Static Memory Controller Byte Lane Strobe Static Memory Controller Chip Select Static Memory Controller Chip Select Static Memory Controller Chip Select Static Memory Controller Chip Select
2 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 2
A[23:0]
Output
Address Signals
1
DMA CONTROLLER (DMAC) DREQ DACK Input Output DMA Request DMA Acknowledge 1 1
Preliminary data sheet
Rev. 01 -- 16 July 2007
19
LH75401/LH75411
NXP Semiconductors
System-on-Chip
Table 5. LH75411 Signal Descriptions (Cont'd)
PIN NO. 120 120 121 122 122 123 124 125 128 128 129 129 130 130 131 132 133 135 136 137 138 139 141 142 143 144 99 100 101 102 104 103 74 76 105 107 89 90 91 92 93 94 95 96 SIGNAL NAME LCDMOD LCDVEEEN LCDVDDEN LCDDSPLEN LCDREV LCDCLS LCDPS LCDDCLK LCDLP LCDHRLP LCDFP LCDSPS LCDEN LCDSPL TYPE Output Output Output Output Output Output Output Output Output Output Output Output Output Output DESCRIPTION COLOR LCD CONTROLLER (CLCDC) Signal Used by the Row Driver (AD-TFT, HR-TFT only) Analog Supply Enable (AC Bias SIgnal) Digital Supply Enable LCD Panel Power Enable Reverse Signal (AD-TFT, HR-TFT only) Clock to the Row Drivers (AD-TFT, HR-TFT only) Power Save (AD-TFT, HR-TFT only) LCD Panel Clock Line Synchronization Pulse (STN), Horizontal Synchronization Pulse (TFT) Latch Pulse (AD-TFT, HR-TFT only) Frame Pulse (STN), Vertical Synchronization Pulse (TFT) Row Driver Counter Reset Signal (AD-TFT, HR-TFT only) LCD Data Enable Start Pulse Left (AD-TFT, HR-TFT only) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 NOTES
LCDVD[11:0]
Output
LCD Panel Data bus
1
SYNCHRONOUS SERIAL PORT (SSP) SSPFRM SSPCLK SSPRX SSPTX UARTRX0 UARTTX0 UARTRX1 UARTTX1 UARTTX2 UARTRX2 AN3 (LR/Y-) AN4 (Wiper) AN9 AN2 (LL/Y+) AN8 AN1 (UR/X-) AN6 AN0 (UL/X+) Output Output Input Output Input Output Input Output Output Input SSP Serial Frame SSP Clock SSP RXD SSP TXD UART0 (U0) UART0 Received Serial Data Input UART0 Transmitted Serial Data Output UART1 (U1) UART1 Received Serial Data Input UART1 Transmitted Serial Data Output UART2 (U2) UART2 Transmitted Serial Data Output UART2 Received Serial Data Input ANALOG-TO-DIGITAL CONVERTER (ADC) 1 1 1 1 1 1 1 1 1 1
Input
ADC Inputs
1
20
Rev. 01 -- 16 July 2007
Preliminary data sheet
System-on-Chip
NXP Semiconductors
LH75401/LH75411
Table 5. LH75411 Signal Descriptions (Cont'd)
PIN NO. 117 116 115 114 113 117 116 118 111 110 111 110 118 109 108 109 108 118 1 2 4 5 6 7 9 10 24 25 27 28 29 30 32 33 35 36 37 38 39 40 72 73 74 76 77 78 79 SIGNAL NAME TYPE TIMER 0 DESCRIPTION NOTES
CTCAP0[A:E]
Input
Timer 0 Capture Inputs
1
CTCMP0[A:B] CTCLK
Output Input
Timer 0 Compare Outputs Common External Clock TIMER 1
1 1
CTCAP1[A:B] CTCMP1[A:B] CTCLK
Input Output Input
Timer 1 Capture Inputs Timer 1 Compare Outputs Common External Clock TIMER 2
1 1 1
CTCAP2[A:B] CTCMP2[A:B] CTCLK PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PB5 PB4 PB3 PB2 PB1 PB0 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PD6 PD5 PD4 PD3 PD2 PD1 PD0
Input Input Input
Timer 2 Capture Inputs Timer 2 Compare Outputs Common External Clock GENERAL PURPOSE INPUT/OUTPUT (GPIO)
1 1 1
Input/Output General Purpose I/O Signals - Port A
1
Input/Output General Purpose I/O Signals - Port B
1
Input/Output General Purpose I/O Signals - Port C
1
Input/Output General Purpose I/O Signals - Port D
1
Preliminary data sheet
Rev. 01 -- 16 July 2007
21
LH75401/LH75411
NXP Semiconductors
System-on-Chip
Table 5. LH75411 Signal Descriptions (Cont'd)
PIN NO. 89 90 91 92 93 94 95 96 99 100 101 102 103 104 105 107 108 109 110 111 113 114 115 116 117 118 120 121 122 123 124 125 128 129 130 131 132 133 135 136 137 138 139 141 142 143 144 62 71 72 73 74 76 77 78 79 SIGNAL NAME PJ7 PJ6 PJ5 PJ4 PJ3 PJ2 PJ1 PJ0 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 PF6 PF5 PF4 PF3 PF2 PF1 PF0 PG7 PG6 PG5 PG4 PG3 PG2 PG1 PG0 PH7 PH6 PH5 PH4 PH3 PH2 PH1 PH0 PI7 PI6 PI5 PI4 PI3 PI2 PI1 PI0 nRESETIN nRESETOUT INT6 INT5 INT4 INT3 INT2 INT1 INT0 TYPE DESCRIPTION NOTES
Input
General Purpose I/O Signals - Port J
1
Input/Output General Purpose I/O Signals - Port E
1
Input/Output General Purpose I/O Signals - Port F
1
Input/Output General Purpose I/O Signals - Port G
1
Input/Output General Purpose I/O Signals - Port H
1
Input/Output General Purpose I/O Signals - Port I
1
RESET, CLOCK, AND POWER CONTROLLER (RCPC) Input Output Input Input Input Input Input Input Input User Reset Input System Reset Output External Interrupt Input 6 External Interrupt Input 5 External Interrupt Input 4 External Interrupt Input 3 External Interrupt Input 2 External Interrupt Input 1 External Interrupt Input 0 2 2 1 1 1 1 1 1 1
22
Rev. 01 -- 16 July 2007
Preliminary data sheet
System-on-Chip
NXP Semiconductors
LH75401/LH75411
Table 5. LH75411 Signal Descriptions (Cont'd)
PIN NO. 81 82 83 86 87 63 64 65 66 67 68 69 3 17 34 42 54 98 112 126 134 8 26 41 48 59 106 119 127 140 11 75 14 80 70 84 85 88 97 NOTES:
1. These pin numbers have multiplexed functions. 2. Signals preceded with `n' are active LOW.
SIGNAL NAME nPOR XTAL32IN XTAL32OUT XTALIN XTALOUT TEST2 TEST1 TMS RTCK TCK TDI TDO
TYPE Input Input Output Input Output Input Input Input Output Input Input Output Power-on Reset Input
DESCRIPTION 32.768 kHz Crystal Clock Input 32.768 kHz Crystal Clock Output Crystal Clock Input Crystal Clock Output TEST INTERFACE Test Mode Pin 2 Test Mode Pin 1 JTAG Test Mode Select Input Returned JTAG Test Clock Output JTAG Test Clock Input JTAG Test Serial Data Input JTAG Test Data Serial Output POWER AND GROUND (GND)
NOTES 2
VDD
Power
I/O Ring VDD
VSS
Power
I/O Ring VSS
VDDC VSSC LINREGEN VSSA_PLL VDDA_PLL VSSA_ADC VDDA_ADC
Power Power Input Power Power Power Power
Core VDD supply (Output if Linear Regulator Enabled, Otherwise Input) Core VSS Linear Regulator Enable PLL Analog VSS PLL Analog VDD Supply A-to-D converter Analog VSS A-to-D converter Analog VDD Supply
Preliminary data sheet
Rev. 01 -- 16 July 2007
23
LH75401/LH75411
NXP Semiconductors
System-on-Chip
LCD
TOUCH SCREEN
CAN TRANSCEIVER CAN NETWORK CAN 2.0B
STN/TFT, AD-TFT/HR-TFT
A/D
FLASH
LH75401
SRAM A/D
UART SENSOR ARRAY
GPIO
SSP
BOOT ROM
1 4 7
2 5 8 0
3 6 9 #
*
SERIAL EEPROM
KEY MATRIX
LH754xx-2A
Figure 4. LH75401 System Application Example
FUNCTIONAL OVERVIEW ARM7TDMI-S Processor
The LH75401/LH75411 microcontrollers feature the ARM7TDMI-S core with an Advanced High-Performance Bus (AHB) 2.0 interface. The ARM7TDMI-S is a 16/32-bit embedded RISC processor and a member of the ARM7 Thumb family of processors. For more information, visit the ARM Web site at www.arm.com.
Power Supplies
Five-Volt-tolerant 3.3 V I/Os are employed. The LH75401/LH75411 microcontrollers require a single 3.3 V supply. The core logic requires 1.8 V, supplied by an on-chip linear regulator. Core logic power may also be supplied externally to achieve higher system speeds. See the Electrical Specifications.
Clock Sources
The LH75401/LH75411 microcontrollers may use two crystal oscillators, or an externally supplied clock. There are two clock trees: * One clock tree drives an internal Phase Lock Loop (PLL) and the three UARTs. It supports a crystal oscillator frequency range from 14 MHz to 20 MHz. * The other is a 32.768 kHz oscillator that generates a 1 Hz clock for the RTC. (Use of the 32.768 kHz crystal for the Real Time Clock is optional. If not using the crystal, tie XTAL32IN to VSS and allow XTAL32OUT to float.) The 14-to-20 MHz crystal oscillator drives the UART clocks, so an oscillator frequency of 14.7456 MHz is recommended to achieve modem baud rates. The PLL may be bypassed and an external clock supplied at XTALIN; the SoC will operate to DC with the PLL disabled. When doing so, allow XTALOUT to float. The input clock with the PLL bypassed will be twice the desired system operating frequency, and care must be taken not to exceed the maximum input clock voltage. Maximum values for system speeds and input voltages are given in the Electrical Specifications.
Bus Architecture
The LH75401/LH75411 microcontrollers use the ARM Advanced Microcontroller Bus Architecture (AMBA) 2.0 internal bus protocol. Three AHB masters control access to external memory and on-chip peripherals: * The ARM processor fetches instructions and transfers data * The Direct Memory Access Controller (DMAC) transfers from memory to memory, from peripheral to memory, and from memory to peripheral * The LCDC refreshes an LCD panel with data from the external memory or from internal memory if the frame buffer is 16 kB or less. The ARM7TDMI-S processor is the default bus master. An Advanced Peripheral Bus (APB) bridge is provided to access to the various APB peripherals. Generally, APB peripherals are serviced by the ARM core. However, if they are DMA-enabled, they are also serviced by the DMAC to increase system performance while the ARM core runs from local internal memory.
24
Rev. 01 -- 16 July 2007
Preliminary data sheet
System-on-Chip
NXP Semiconductors
LH75401/LH75411
Reset Generation
EXTERNAL RESETS Two external signals generate resets to the ARM7TDMI-S core: * nPOR sets all internal registers to their default state when asserted. It is used as a Power-On Reset. * nRESETIN sets all internal registers, except the JTAG circuitry, to their default state when asserted. When nPOR is asserted, nRESETIN defines the microcontroller Test Mode. When nPOR is released, nRESETIN behaves during Reset as described previously. INTERNAL RESETS There are two types of Internal Resets generated: * System Reset * RTC Reset. System and RTC Resets are asserted by: * An External Reset (a logic LOW signal on the external nRESETIN or nPOR input pin) * A signal from the internal Watchdog Timer * A Soft Reset. The reset latency depends on the PLL lock state.
Memory Interface Architecture
The LH75401/LH75411 microcontrollers provide the following data-path management resources on chip: * AHB and APB data buses * 16 kB of zero-wait-state TCM SRAM accessible via processor * 16 kB of internal SRAM accessible via processor, DMAC, and LCDC * A Static Memory Controller (SMC) that controls access to external memory * A 4-stream general-purpose DMAC. All external and internal system resources are memory-mapped. This memory map partition has three views, based on the setting of the REMAP bits in the Reset, Clock, and Power Controller (RCPC). The second partitioning of memory space is the dividing of the segments into sections. The external memory segment is divided into eight 64 MB sections, of which the first four are used, each having a chip select associated with it. Access to any of the last four sections does not result in an external bus access and does not cause a memory abort. The peripheral register segment is divided into 4 kB peripheral sections, 21 of which are assigned to peripherals. Table 7. Memory Mapping
ADDRESS 0x00000000 0x20000000 0x40000000 0x60000000 REMAP = 00 REMAP = 01 REMAP = 10 (DEFAULT) External Memory Reserved External Memory Internal SRAM TCM SRAM Reserved Reserved Reserved Internal SRAM Reserved External Memory Internal SRAM TCM SRAM Reserved Reserved Reserved TCM SRAM Reserved External Memory Internal SRAM TCM SRAM Reserved Reserved Reserved
AHB Master Priority and Arbitration
The LH75401/LH75411 microcontrollers have three AHB masters: * ARM processor * DMAC * LCD Controller. Each AHB master has a priority level that is permanent and cannot change. Table 6. Bus Master Priority
PRIORITY 1 (Highest) 2 3 (Lowest) BUS MASTER PRIORITY Color LCDC (LH75401 and LH75411) DMAC ARM7TDMI-S Core (Default)
0x80000000 0xA0000000 0xC0000000 0xE0000000 0xFFFBFFFF
Preliminary data sheet
Rev. 01 -- 16 July 2007
25
LH75401/LH75411
NXP Semiconductors
System-on-Chip
Table 8. APB Peripheral Register Mapping
ADDRESS RANGE DEVICE
* Supports memory-mapped devices, including Random Access Memory (RAM), Read Only Memory (ROM), Flash, and burst ROM * Supports external bus and external device widths of 8 and 16 bits * Supports Asynchronous Burst Mode read access for Burst Mode ROM devices, with up to 32 independent wait states for read and write accesses * Supports indefinite extended wait states via an external hardware pin (nWAIT) * Supports varied bus turnaround cycles (1 to 16) between a read and write operation
0xFFFC0000 - 0xFFFC0FFF UART0 (16550) 0xFFFC1000 - 0xFFFC1FFF UART1 (16550) 0xFFFC2000 - 0xFFFC2FFF UART2 (82510) 0xFFFC3000 - 0xFFFC3FFF Analog-to-Digital Converter 0xFFFC4000 - 0xFFFC4FFF Timer Module 0xFFFC5000 - 0xFFFC5FFF CAN (LH75401) Reserved (LH75411)
0xFFFC6000 - 0xFFFC6FFF Synchronous Serial Port 0xFFFC7000 - 0xFFFDAFFF Reserved 0xFFFDB000 - 0xFFFDBFFF GPIO4 0xFFFDC000 - 0xFFFDCFFF GPIO3 0xFFFDD000 - 0xFFFDDFFF GPIO2 0xFFFDE000 - 0xFFFDEFFF GPIO1 0xFFFDF000 - 0xFFFDFFFF GPIO0 0xFFFE0000 - 0xFFFE0FFF Real Time Clock 0xFFFE1000 - 0xFFFE1FFF DMAC 0xFFFE2000 - 0xFFFE2FFF Reset Clock and Power Controller
Direct Memory Access Controller (DMAC)
One central DMAC services all peripheral DMA requirements for the DMA-capable peripherals listed in Table 9. The DMA is controlled by the system clock. It has an APB slave port for programming of its registers and an AHB port for data transfers. Table 9. DMAC Stream Assignments
DMA REQUEST SOURCE UART1RX (highest priority) UART1TX UART0RX/External Request (DREQ) UART0TX (lowest priority) DMA STREAM Stream0 Stream1 Stream2 Stream3
0xFFFE3000 - 0xFFFE3FFF Watchdog Timer 0xFFFE4000 - 0xFFFE4FFF Advanced LCD Interface 0xFFFE5000 - 0xFFFE5FFF I/O Configuration Peripheral 0xFFFE6000 - 0xFFFEFFFF Reserved
Static Random Access Memory Controller
The LH75401/LH75411 microcontrollers have 32 kB of Static Random Access Memory (SRAM) organized into two 16 kB blocks: * 16 kB of TCM 0 Wait State SRAM is available to the processor as an ARM7TDMI-S bus slave. * 16 kB of internal SRAM is available as an AHB slave and accessible via processor, DMAC, and LCDC. Each memory segment is 512 MB, though the TCM and internal SRAMs are 16 kB each in size. Any access beyond the first 16 kB is mapped to the lower 16 kB, but does not cause a data or prefetch abort.
DMAC FEATURES * Four data streams that can be used to service: - Four peripheral data streams (peripheral-tomemory or memory-to-peripheral) - Three peripheral data streams and one memoryto-memory data stream. * Three transfer modes: - Memory to Memory (selectable on Stream3) - Peripheral to Memory (all streams) - Memory to Peripheral (all streams). * Built-in data stream arbiter * Seven programmable registers for each stream * Ability for each stream to indicate a transfer error via an interrupt * 16-word First-In, First Out (FIFO) array, with pack and unpack logic to handle all input/output combinations of byte, half-word, and word transfers * APB slave port allows the ARM core to program DMAC registers * AHB port for data transfers.
Static Memory Controller (SMC)
The Static Memory Controller (SMC) is an AMBA AHB slave peripheral that provides the interface between the LH75401/LH75411 microcontrollers and external memory devices. SMC FEATURES * Provides four banks of external memory, each with a maximum size of 16 MB.
26
Rev. 01 -- 16 July 2007
Preliminary data sheet
System-on-Chip
NXP Semiconductors
LH75401/LH75411
Color LCD Controller (CLCDC)
The CLCDC is an AMBA master-slave module that connects to the AHB. It translates pixel-coded data into the required formats and timings to drive single/dual monochrome and color LCD panels. Packets of pixelcoded data are fed, via the AHB interface, to two independently programmable, 32-bit-wide DMA FIFOs. Each FIFO is 16 words deep by 32 bits wide. The CLCDC generates a single combined interrupt to the Vectored Interrupt Controller (VIC) when an interrupt condition becomes true for upper/lower panel DMA FIFO underflow, base address update signification, vertical compare, or bus error.
NOTE: LH75401 and LH75411 microcontrollers support full-color operation.
ADVANCED LCD INTERFACE The Advanced LCD Interface (ALI) allows for direct connection to ultra-thin panels that do not include a timing ASIC. It converts TFT signals from the Color LCD controller to provide the proper signals, timing and levels for direct connection to a panel's Row and Column drivers for AD-TFT, HR-TFT, or any technology of panel that allows for a connection of this type. The ALI also provides a bypass mode that allows interfacing to the builtin timing ASIC in standard TFT and STN panels.
NOTES: 1. The Advanced LCD Interface pertains to the LH75401 and LH75411 microcontrollers. 2. VGA and XGA modes require 66 MHz core speed.
CLCDC FEATURES * STN, Color STN, TFT, HR-TFT, and AD-TFT - Fully Programmable Timing Controls - Advanced LCD Interface for displays with a low level of integration, such as HR-TFT and AD-TFT * Programmable Resolution - Up to VGA (640 x 480 DPI), 12-bit Direct Mode Color - Up to SVGA (800 x 600 DPI), 8-bit Direct/Palettized Color - Up to XGA (1,024 x 768 DPI), 4-bit Direct Color/ Grayscale - Direct or Palettized Colors * Single and Dual Panels * Supports Sharp and non-Sharp Panels * CLCDC Outputs Available as General Purpose Inputs/Outputs (GPIOs) if LCDC is Not Needed * Additional Features - Fully programmable horizontal and vertical timing for different display panels - 256-entry, 16-bit palette RAM physically arranged as a 128 x 32-bit RAM - AC bias signal for STN panels and a data-enable signal for TFT panels. * Programmable Panel-related Parameters - STN mono/color or TFT display - Bits-per-pixel - STN 4- or 8-bit Interface Mode - STN Dual or Single Panel Mode - AC panel bias - Panel clock frequency - Number of panel clocks per line - Signal polarity, active HIGH or LOW - Little Endian data format - Interrupt-generation event.
Universal Asynchronous Receiver Transmitters (UARTs)
The LH75401/LH75411 microcontrollers incorporate three UARTs, designated UART0, UART1, and UART2. UART 0 AND 1 FEATURES * Similar functionality to the industry-standard 16C550 * Supported baud rates up to 921,600 baud (given an external crystal frequency of 14.756 MHz) * Supported character formats: - Data bits per character: 5, 6, 7, or 8 - Parity generation and detection: Even, odd, stick, or none - Stop bit generation: 1 or 2 * Full-duplex operation * Separate transmit and receive FIFOs, with: - Programmable depth (1 to 16) - Programmable-service `trigger levels' (1/8, 1/4, 1/2, 3/4, and 7/8) - Overrun protection. * Programmable baud-rate generator that: - Enables the UART input clock to be divided by 16 to 65,535 x 16 - Generates an internal clock common to both transmit and receive portions of the UART. * DMA support * Support for generating and detecting breaks during UART transactions * Loopback testing.
Preliminary data sheet
Rev. 01 -- 16 July 2007
27
LH75401/LH75411
NXP Semiconductors
System-on-Chip
UART 2 FEATURES * Similar functionality to the industry-standard 82510 * Supported baud rates up to 3,225,600 baud (given a system clock of 51.6096 MHz) * 5, 6, 7, 8, or 9 data bits per character * Even, odd, HIGH, LOW, software, or no parity-bit generation and detection * 3/4, 1, 1-1/4, 1-1/2, 1-3/4, or 2 stop-bit generation * LAN address flag * Full-duplex operation * Separate transmit and receive FIFOs, with programmable depth (1 or 4). Each FIFO has overrun protection and: - Programmable receive trigger levels: 1/4, 1/2, 3/4, or full - Programmable transmit trigger levels: empty, 1/4, 1/2, 3/4. * Two 16-bit baud-rate generators. * One interrupt that can be triggered by transmit and receive FIFO thresholds, receive errors, control character or address marker reception, or timer timeout * Generation and detection of breaks during UART transactions * Support for local loopback, remote loopback, and auto-echo modes * LAN Address Mode.
The timers support a PWM Mode that uses the two Timer Compare Registers associated with a timer to create a PWM. Each timer can generate a separate interrupt. The interrupt becomes active if any enabled compare, capture, or overflow interrupt condition occurs. The interrupt remains active until all compare, capture, and overflow interrupts are cleared.
Real Time Clock (RTC)
The RTC is an AMBA slave module that connects to the APB. The RTC provides basic alarm functions or acts as a long-time base counter by generating an interrupt signal after counting for a programmed number of cycles of an RTC input. Counting in 1-second intervals is achieved using a 1 Hz clock input to the RTC. RTC FEATURES * 32-bit up-counter with programmable load * Programmable 32-bit match Compare Register * Software-maskable interrupt that is set when the Counter and Compare Registers have identical values.
Controller Area Network (CAN)
The CAN 2.0B Controller is an AMBA-compliant peripheral that connects as a slave to the APB. The CAN Controller is located between the processor core and a CAN Transceiver, and is accessed through the AMBA port. CAN communications are performed serially, at a maximum frequency of 1 MB/s, using the TX (transmit) and RX (receive) lines. The TX and RX signals for data transmission and reception provide the communications interface between the CAN Controller and the CAN bus. All peripherals share the TX and RX lines, and always see the common incoming and outgoing data. Bus arbitration follows the CAN 2.0A and CAN 2.0B specifications. The bus is always controlled by the node with the highest priority (lowest ID). Only after the bus has been released can the next highest priority node control it. Transmit and receive errors are handled according to the CAN protocol. Bus timing is critical to the CAN protocol. Therefore, the CAN Controller has two programmable Bus Timing Registers that define timing parameters.
NOTE: The CAN Controller pertains to the LH75401 microcontrollers.
Timers
The LH75401/LH75411 microcontrollers have three 16-bit timers. The timers are clocked by the system clock, but have an internal scaled-down system clock that is used for the Pulse Width Modulator (PWM) and compare functions. All counters are incremented by an internal prescaled counter clock or external clock and can generate an overflow interrupt. All three timers have separate internal prescaled counter clocks, with either a common external clock or a prescaled version of the system clock. * Timer 0 has five Capture Registers and two Compare Registers. * Timer 1 and Timer 2 have two Capture and two Compare Registers each. The Capture Registers have edge-selectable inputs and can generate an interrupt. The Compare Registers can force the compare output pin either HIGH or LOW upon a match.
28
Rev. 01 -- 16 July 2007
Preliminary data sheet
System-on-Chip
NXP Semiconductors
LH75401/LH75411
CAN 2.0B FEATURES * Full compliance with 2.0A and 2.0B Bosch specifications * Supports 11-bit and 29-bit identifiers * Supports bit rates up to 1Mbit/s * 64-byte receive FIFO * Software-driven bit-rate detection for hot plug-in support * Single-shot transmission option * Acceptance filtering * Listen Only Mode * Reception of `own' messages * Error interrupt generated for each CAN bus error * Arbitration-lost interrupt with record of bit position * Read/write error counters * Last error register * Programmable error-limit warning.
* Touch-pressure sensing circuits * Pen-down sensing circuit and interrupt generator * Voltage-reference generator that is independently controlled * Conversion automation function to minimize controller interrupt overhead * Brownout Detector.
Synchronous Serial Port (SSP)
The SSP is a master-only interface for synchronous serial communication with slave peripheral devices that have a Motorola SPI, National Semiconductor Microwire, or Texas Instruments DSP-compatible Synchronous Serial Interface (SSI). The SSP performs serial-to-parallel conversion on data received from a peripheral device. The transmit and receive paths are buffered with internal FIFO memories. These memories store eight 16-bit values independently in both transmit and receive modes. During transmission: * Data writes to the transmit FIFO via the APB interface. * The transmit data is queued for parallel-to-serial conversion onto the transmit interface. * The transmit logic formats the data into the appropriate frame type: - Motorola SPI - National Semiconductor Microwire - Texas Instruments DSP-compatible SSI. SSP FEATURES * SSI in Master Only Mode. The SSP performs serial communications as a master device in one of three modes: - Motorola SPI - Texas Instruments DSP-compatible synchronous serial interface - National Semiconductor Microwire. * Two 16-bit-wide, 8-entry-deep FIFOs, one for data transmission and one for data reception. * Supports interrupt-driven data transfers that are greater than the FIFO watermark. * Programmable clock bit rate. * Programmable data frame size, from 4 to 16 bits long, depending on the size of data programmed. Each frame transmits starting with the most-significant bit. * Four interrupts, each of which can be individually enabled or disabled using the SSP Control Register bits. A combined interrupt is also generated as an OR function of the individual interrupt requests. * Loopback Test Mode.
Analog-to-Digital Converter (ADC)/ Brownout Detector
The ADC is an AMBA-compliant peripheral that connects as a slave to the APB. The ADC block consists of an 8-channel, 10-bit Analog-to-Digital Converter with integrated Touch Screen Controller. The complete Touch Screen interface is achieved by combining the front-end biasing, control circuitry with analog-to-digital conversion, reference generation, and digital control. The ADC also has a programmable measurement clock derived from the system clock. The clock drives the measurement sequencer and the successiveapproximation circuitry. The ADC includes a Brownout Detector. The Brownout Detector is an asynchronous comparator that compares a divided version of the 3.3 V supply and a bandgap-derived reference voltage. If the supply dips below a Trip point, the Brownout Detector sets a status register bit. The status bit is wired to the VIC and can interrupt the processor core. This allows the Host Controller to warn users of an impending shutdown and may provide the ADC with sufficient time to save its state. ADC/BROWNOUT DETECTOR FEATURES * 10-bit fully differential Successive Approximation Register (SAR) with integrated sample/hold * 8-channel multiplexer for routing user-selected inputs to the ADC in Single Ended and Differential Modes * 16-entry x 16-bit-wide FIFO that holds the 10-bit ADC output and a 4-bit tag number * Front bias-and-control network for Touch Screen interface and support functions compatible with industry-standard 4- and 5-wire touch-sensitive panels
Preliminary data sheet
Rev. 01 -- 16 July 2007
29
LH75401/LH75411
NXP Semiconductors
System-on-Chip
Table 10. SSP Modes MODE Motorola SPI SSI DESCRIPTION DATA TRANSFERS
For communications with Motorola SPI-compatible Full-duplex, 4-wire devices. Clock polarity and phase are programmable. synchronous For communications with Texas Instruments DSPcompatible Serial Synchronous Interface devices. Full-duplex, 4-wire synchronous Half-duplex synchronous, using 8-bit control messages
National Semiconductor For communications with National Semiconductor Microwire Microwire-compatible devices.
Watchdog Timer (WDT)
The WDT consists of a 32-bit down-counter that allows a selectable time-out interval to detect malfunctions. The timer must be reset by software periodically. Otherwise, a time-out occurs, interrupting the system. If the interrupt is not serviced within the timeout period, the WDT triggers the RCPC to generate a System Reset. If the WDT times out, it sets a bit in the RCPC Reset Status Register. The WDT supports 16 selectable time intervals, for a time-out of 216 through 231 system clock cycles. All Control and Status Registers for the Watchdog Timer are accessed through the APB.
WDT FEATURES * Counter generates an interrupt at a set interval and the count reloads from the pre-set value after reaching zero. * Default timeout period is set to the minimum timeout of 216 system clock cycles. * WDT is driven by the APB. * Built-in protection mechanism interrupt-service failure. guards against
* WDT can be programmed to trigger a System Reset on a timeout. * WDT can be programmed to trigger an interrupt on the first timeout; then, if the service routine fails to clear the interrupt, the next WDT timeout triggers a System Reset.
30
Rev. 01 -- 16 July 2007
Preliminary data sheet
System-on-Chip
NXP Semiconductors
LH75401/LH75411
Vectored Interrupt Controller (VIC)
All internal and external interrupts are routed to the VIC, where hardware determines the interrupt priority (see Table 11). The VIC is also where the appropriate signal to the processor (IRQ or FIQ) is generated. The processor services the interrupt as either a vectored interrupt or a default-vectored interrupt. The VIC accepts inputs from 32 interrupt source lines: * Seven external * Twenty-three internal * Two used as software interrupts. All 32 interrupt source lines can be enabled, disabled, and cleared individually, and individual status can be determined. On reset, all interrupts are disabled.
The VIC also accepts software-generated interrupts. Software-generated interrupts use the same enabling control as hardware-generated interrupts. The VIC provides 32 interrupts: * 16 vectored interrupts * 16 or more default-vectored interrupts. Any of the 32 interrupt source lines can be assigned to any of the 16 interrupt vectors. Any line not explicitly assigned to an interrupt vector is processed as a default-vectored interrupt. At reset, all 32 lines become default-vectored interrupts. Each interrupt line can be explicitly identified as an IRQ (default) or FIQ interrupt. Vectored-interrupt servicing is only available for IRQ interrupts.
Table 11. Interrupt Channels
POSITION 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 DESCRIPTION WDT Not Used ARM7 DBGCOMMRX ARM7 DBGCOMMTX Timer0 Combined Timer1 Combined Timer2 Combined External Interrupt 0 External Interrupt 1 External Interrupt 2 External Interrupt 3 External Interrupt 4 External Interrupt 5 External Interrupt 6 Not Used RTC_ALARM ADC TSCIRQ (combined) ADC BrownOutINTR ADC PenIRQ LCD SSPTXINTR SSPRXINTR SSPRORINTR SSPRXTOINTR SSPINTR UART1 UARTRXINTR UART1 UARTTXINTR UART1 UARTINTR UART0 UARTINTR UART2 Interrupt DMA CAN SOURCE Watchdog Timer Available as a software interrupt Sourced by the ARM7TDMI-S Core Sourced by the ARM7TDMI-S Core Timer0 Timer1 Timer2 Sourced by the GPIO Block Sourced by the GPIO Block Sourced by the GPIO Block Sourced by the GPIO Block Sourced by the GPIO Block Sourced by the GPIO Block Sourced by the GPIO Block Available as a software interrupt Real Time Clock Analog-to-Digital Converter Brown Out Detector Analog-to-Digital Converter LCD Controller Synchronous Serial Port Synchronous Serial Port Synchronous Serial Port Synchronous Serial Port Synchronous Serial Port UART1 UART1 UART1 UART0 UART2 DMA CAN (LH75401) Reserved (LH75411)
Preliminary data sheet
Rev. 01 -- 16 July 2007
31
LH75401/LH75411
NXP Semiconductors
System-on-Chip
Reset, Clock, and Power Controller (RCPC)
The RCPC lets users control System Reset, clocks, power management, and external interrupt conditioning via the AMBA APB interface. This control includes: * Enabling and disabling various clocks * Managing power-down sequencing * Selecting the sources for various clocks. The RCPC provides for an orderly start-up until the crystal oscillator stabilizes and the PLL acquires lock. If users want to change the system clock frequency during normal operation, the RCPC ensures a seamless transition between the old and new frequencies. RCPC FEATURES * Manages five Power Modes for minimizing power consumption: Active, Standby, Sleep, Stop1, and Stop2 * Generates the system clock (HCLK) from either the PLL clock or the PLL-bypassed (oscillator) clock, divided by 2, 4, 6, 8, ... 30 * Generates three UART clocks from oscillator clock * Generates the 1 Hz RTC clock * Generates the SSP and LCD clocks from HCLK, divided by 1, 2, 4, 8, 16, 32, or 64 * Provides a selectable external clock output * Generates system and RTC Resets based on an external reset, Watchdog Timer reset, or soft reset * Configures seven HIGH/LOW-level or rising/falling edge-trigger external interrupts and converts them to HIGH-level trigger interrupt outputs required by the VIC * Generates remap outputs used by the memory map decoder * Provides an identification register * Supports external or watchdog reset status.
The state of the TEST1, TEST2, and nRESETIN signals determines the operating mode entered at Poweron Reset (see Table 12). Table 12. Device Operating Modes
OPERATING MODE Reserved PLL Bypass Reserved Reserved EmbeddedICE Normal TEST2 0 0 0 1 1 1 TEST1 0 0 1 0 0 1 nRESETIN 0 1 x 0 1 x
NOTE: TEST1, TEST2, and nRESETIN are latched on the rising edge of nPOR. The microcontroller stays in that operating mode until power is removed or nPOR transitions from LOW to HIGH.
General Purpose Input/Output (GPIO)
The LH75401/LH75411 microcontrollers have 10 GPIO ports: * Seven 8-bit ports * Two 7-bit ports * One 6-bit port. The GPIO ports are designated A through J and provide 76 bits of programmable input/output (see Table 13). Pins of all ports, except Port J, can be configured as inputs or outputs. Port J is input only. Upon System Reset, all ports default to inputs. Table 13. GPIO Ports
PORT A B C D E F G H I J PROGRAMMABLE PINS 8 Input/Output Pins 6 Input/Output Pins 8 Input/Output Pins 7 Input/Output Pins 8 Input/Output Pins 7 Input/Output Pins 8 Input/Output Pins 8 Input/Output Pins 8 Input/Output Pins 8 Input Pins
Operating Modes
The LH75401/LH75411 microcontrollers support three operating modes: * Normal Mode * PLL Bypass Mode, where the internal PLL is bypassed and an external clock source is used; otherwise the chip operates normally * EmbeddedICE Mode, where the JTAG port accesses the TAP Controller in the core and the core is placed in Debug Mode.
32
Rev. 01 -- 16 July 2007
Preliminary data sheet
System-on-Chip
NXP Semiconductors
LH75401/LH75411
Device Pin Multiplexing
Table 14. LCD Panel Signal Multiplexing EXTERNAL PIN LVCVD11 LVCVD10 LVCVD9 LVCVD8 LVCVD7 LVCVD6 LVCVD5 LVCVD4 LVCVD3 LVCVD2 LVCVD1 LVCVD0 4-BIT STN (MONOCHROME) SINGLE PANEL Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved MUSTN3 MUSTN2 MUSTN1 MUSTN0 DUAL PANEL MLSTN3 MLSTN2 MLSTN1 MLSTN0 Reserved Reserved Reserved Reserved MUSTN3 MUSTN2 MUSTN1 MUSTN0 8-BIT STN SINGLE PANEL (MONOCHROME) Reserved Reserved Reserved Reserved MUSTN7 MUSTN6 MUSTN5 MUSTN4 MUSTN3 MUSTN2 MUSTN1 MUSTN0
NOTES: 1. MUSTN = Mono upper panel STN, dual and/or single panel. 2. MLSTN = Mono lower panel STN, dual panel only.
Table 15. LCD External Pin Multiplexing (LH75401 and LH75411)
EXTERNAL PIN PG4/LCDVEEEN/LCDMOD PG3/LCDVDDEN PG2/LCDDSPLEN/LCDREV PG1/LCDCLS PG0/LCDPS PH7/LCDDCLK PH6/LCDLP/LCDHRLP PH5/LCDFP/LCDSPS PH4/LCDEN/LCDEN PH3/LCDVD11 PH2/LCDVD10 PH1/LCDVD9 PH0/LCDVD8 PI7/LCDVD7 PI6/LCDVD6 PI5/LCDVD5 PI4/LCDVD4 PI3/LCDVD3 PI2/LCDVD2 PI1/LCDVD1 PI0/LCDVD0 DEFAULT MODE (NO LCD) PG4 PG3 PG2 PG1 PG0 PH7 PH6 PH5 PH4 PH3 PH2 PH1 PH0 PI7 PI6 PI5 PI4 PI3 PI2 PI1 PI0 4-BIT MONO STN MODE SINGLE LCDVEEEN LCDVDDEN LCDDSPLEN PG1 PG0 LCDDCLK LCDLP LCDFP LCDEN PH3 PH2 PH1 PH0 PI7 PI6 PI5 PI4 MUSTN3 MUSTN2 MUSTN1 MUSTN0 DUAL LCDVEEEN LCDVDDEN LCDDSPLEN PG1 PG0 LCDDCLK LCDLP LCDFP LCDEN MLSTN3 MLSTN2 MLSTN1 MLSTN0 PI7 PI6 PI5 PI4 MUSTN3 MUSTN2 MUSTN1 MUSTN0 8-BIT STN MODE LCDVEEEN LCDVDDEN LCDDSPLEN PG1 PG0 LCDDCLK LCDLP LCDFP LCDEN PH3 PH2 PH1 PH0 STN7 STN6 STN5 STN4 STN3 STN2 STN1 STN0 TFT MODE LCDVEEEN LCDVDDEN LCDDSPLEN PG1 PG0 LCDDCLK LCDLP LCDFP LCDEN LCDVD11 LCDVD10 LCDVD9 LCDVD8 LCDVD7 LCDVD6 LCDVD5 LCDVD4 LCDVD3 LCDVD2 LCDVD1 LCDVD0 ALI MODE LCDMOD LCDVDDEN LCDREV LCDCLS LCDPS LCDDCLK LCDLP LCDFP LCDEN LCDVD11 LCDVD10 LCDVD9 LCDVD8 LCDVD7 LCDVD6 LCDVD5 LCDVD4 LCDVD3 LCDVD2 LCDVD1 LCDVD0
Preliminary data sheet
Rev. 01 -- 16 July 2007
33
LH75401/LH75411
NXP Semiconductors
System-on-Chip
ELECTRICAL SPECIFICATIONS
Table 16. Absolute Maximum Ratings PARAMETER DC Core Supply Voltage (VDDC) DC I/O Supply Voltage (VDD) DC Analog Supply Voltage for ADC (VDDA0) DC Analog Supply Voltage for PLL (VDDA1) Storage Temperature (TSTG) MINIMUM MAXIMUM -0.3 V -0.3 V -0.3 V -0.3 V -55C 2.4 V 4.6 V 4.6 V 2.4 V 125C
NOTE: These ratings are only for transient conditions. Operation at or beyond absolute maximum rating conditions may affect reliability and cause permanent damage to the device.
Table 17. Recommended Operating Conditions PARAMETER DC Core Supply Voltage (VDDC) (Linear Regulator disabled) DC Analog Supply Voltage for ADC (VDDA0) DC I/O Supply Voltage (VDD) DC Analog Supply Voltage for PLL (VDDA1) Clock Frequency (HCLK) Clock Period (tHCLK) Crystal Frequency Industrial Operating Temperature MINIMUM 1.7 V 3.0 V 3.0 V 1.7 V 4.375 MHz 11.9047 ns 14 MHz -40C 25C TYP. 1.8 V 3.3 V 3.3 V 1.8 V MAXIMUM 1.98 V 3.6 V 3.6 V 1.98 V 84 MHz 228.571 ns 20 MHz 85C 1 2 3, 4, 5 3, 4, 5 4, 5 NOTES 1
NOTES: 1. Core Voltage should never exceed I/O Voltage after initial power up. See the section titled `Power Supply Sequencing'. 2. Connect VDDA1 to VDDC when using the on-chip linear regulator. 3. On-chip Linear regulator enabled. When the on-chip linear regulator is enabled, Core power is drawn from VDD - allow VDDC pins to float. 4. Will operate to DC with PLL disabled. Core frequencies greater than 84 MHz require external clock and VDDC. Core frequencies faster than 70 MHz require an externally-supplied clock. 5. Processor is functional at minimum frequency, but not all peripherals may be enabled. 6. The maximum operating frequency is the crystal frequency x 3.5.
Table 18. Clock Frequency vs. Voltages (VDDC) vs. Temperature
PARAMETER 25C 70C 85C Clock Frequency (HCLK) Clock Period (tHCLK) Clock Frequency (HCLK) Clock Period (tHCLK) Clock Frequency (HCLK) Clock Period (tHCLK) 1.7 V 91.3 MHz 10.952 ns 86 MHz 11.627 ns 84 MHz 11.9047 ns 1.8 V 97 MHz 10.309 ns 92 MHz 10.869 ns 90 MHz 11.111 ns 1.9 V 103.7 MHz 9.643 ns 97.4 MHz 10.266 ns 95.2 MHz 10.504 ns
NOTES: 1. On-chip Linear regulator and PLL disabled; VDDC supplied externally. 2. Core speeds greater than 84 MHz require external VDDC and may not yield proper UART baud rates. 3. Core speeds greater than 70 MHz require an external clock. 4. Additional performance may be achieved in accordance with Figure 5.
34
Rev. 01 -- 16 July 2007
Preliminary data sheet
System-on-Chip
NXP Semiconductors
LH75401/LH75411
110
105
100 2V
Frequency (MHz)
95
1.95 V 1.9 V
90
1.85 V 1.8 V
85
1.75 V 1.7 V
80
1.65 V 1.6 V
75
70 25 35 45 55 65 75 85
Temp (Celsius)
LH754xx-106
Figure 5. Maximum Core Frequency versus Voltage and Temperature
Very Low Operating Temperatures and Noise Immunity
The junction temperature, Tj, is the operating temperature of the transistors in the integrated circuit. The switching speed of the CMOS circuitry within the SoC depends partly on Tj, and the lower the operating temperature, the faster the CMOS circuits will switch. Increased switching noise generated by faster switching circuits could affect the overall system stability. The amount of switching noise is directly affected by the application executed on the SoC. NXP recommends that users implementing a system to meet low industrial temperature standards should use an external oscillator rather than a crystal to drive the system clock input of the System-on-Chip. This change from crystal to oscillator will increase the robustness (i.e., noise immunity of the clock input to the SoC.
Preliminary data sheet
Rev. 01 -- 16 July 2007
35
LH75401/LH75411
NXP Semiconductors
System-on-Chip
DC Characteristics
All characteristics are specified over an operating temperature of -40C to +85C, and at minimum and maximum supply voltages. Table 19. DC Characteristics SYMBOL VIH VIL VT+ VTVhst PARAMETER CMOS Input HIGH Voltage CMOS Input LOW Voltage Schmitt Trigger Positive Going Threshold Schmitt Trigger Negative Going Threshold Schmitt Trigger Hysteresis Output Drive 1 VOH Output Drive 2 Output Drive 3 Output Drive 4 Output Drive 1 VOL Output Drive 2 Output Drive 3 Output Drive 4 XTAL32IN XTALIN IIN IACTIVE ISLEEP ISTOP1 ISTOP2 ISTOP2 External Clock Input External Clock Input Input Leakage Current Active Current Sleep Current Stop1 Current Stop2 Current (RTC ON) Stop2 Current (RTC OFF) 1.62 1.62 -10 50 45 4.0 3.0 35 120 23 100 1.8 1.8 0.35 2.6 2.6 2.6 2.6 0.4 0.4 0.4 0.4 1.98 1.98 10 70 2.0 0.8 MIN. TYP. MAX. UNIT 2.0 0.8 V V V V V V V V V V V V V V V A mA mA mA mA A A A A 3 4 3 4 IOH = -2 mA IOH = -4 mA IOH = -6 mA IOH = -8 mA IOL = 2 mA IOL = 4 mA IOL = 6 mA IOL = 8 mA Externally supplied Externally supplied VIN = VDD or GND 2 2 1 CONDITIONS NOTES
ISTANDBY Standby Current
NOTES: 1. VIL MAX. = 0.5 V for pin TCK with 50 pF load. 2. Running a Typical Application at 51.6 MHz.
3. Using external 1.8 V supply, internal regulator disabled. 4. Using Internal linear regulator.
Table 20. Linear Regulator DC Characteristics
SYMBOL IQUIESCENT ISLEEPLR IOLR VOLR RPULL PARAMETER Quiescent Current Current when Regulator is Disabled Output Current Range Output Voltage Pull-up Resistor 0.0 1.84 0 MIN. TYP. 75 8 100 MAX. UNIT A A mA V
36
Rev. 01 -- 16 July 2007
Preliminary data sheet
System-on-Chip
NXP Semiconductors
LH75401/LH75411
Analog-To-Digital Converter Electrical Characteristics
Table 21 shows the derated specifications for extended temperature operation. See Figure 6 for the ADC transfer characteristics. Table 21. ADC Electrical Characteristics at Industrial Operating Range PARAMETER A/D Resolution Throughput Conversion Acquisition Time Clk Period Differential Non-Linearity Integral Non-Linearity Offset Error Gain Error On-chip Voltage Reference (VREF) Negative Reference Input (VREF-) Positive Reference Input (VREF+) Crosstalk between channels Analog Input Voltage Range Analog Input Current Reference Input Current Analog input capacitance Operating Supply Voltage Operating Current, VDDA Standby Current Stop Current, VDDA Brown Out Trip Point Brown Out Hysterisis Operating Temperature -40 3.0 590 180 <1 2.63 120 85 0 MIN. 10 17 3 500 -0.99 -3.5 -35 -4.0 1.85 VSSA (VREF-) +1.0 2.0 VSSA VREF -60 VDDA 5 5 15 3.6 5,000 4.5 +3.5 +35 4.0 2.15 (VREF+) -1.0 VDDA TYP. MAX. 10 UNITS Bits CLK Cycles CLK Cycles ns LSB LSB mV LSB V V V dB V A A pF V A A A V mV C 4 3 2 2 1 NOTES
NOTES: 1. The analog section of the ADC takes 16 x A2DCLK cycles per conversion, plus 1 x A2DCLK cycles to be made available in the PCLK domain. An additional 3 x PCLK cycles are required before being available on the APB. 2. The internal voltage reference is driven to nominal value VREF = 2.0 V. Using the Reference Multiplexer, alternative low impedance (RS < 500) voltages can be selected as reference voltages. The range of voltages allowed are specified above. However, the on-chip reference cannot drive the ADC unless the reference buffer is switched on. 3. The analog input pins can be driven anywhere between the power supply rails. If the voltage at the input to the ADC exceeds VREF+ or is below VREF-, the A/D result will saturate appropriately at positive or negative full scale. Trying to pull the analog input pins above or below the power supply rails will cause protection diodes to be forward-biased, resulting in large current source/sink and possible damage to the ADC. 4. Bandgap and other low-bandwidth circuitry operating. All other ADC blocks shut down.
Preliminary data sheet
Rev. 01 -- 16 July 2007
37
LH75401/LH75411
NXP Semiconductors
System-on-Chip
OFFSET GAIN ERROR ERROR
1024 1023 1022 1021 1020 1019 1018 IDEAL TRANSFER CURVE
9 8 7 6 5 4 3 2 1 1 2 3 4 5 6 7 8 9 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 CENTER OF A STEP OF THE ACTUAL TRANSFER CURVE
ACTUAL TRANSFER CURVE
INTEGRAL NON-LINEARITY
OFFSET ERROR
LSB DNL
754xx-54
Figure 6. ADC Transfer Characteristics
38
Rev. 01 -- 16 July 2007
Preliminary data sheet
System-on-Chip
NXP Semiconductors
LH75401/LH75411
POWER SUPPLY SEQUENCING When using an external 1.8 V supply (instead of the internal 1.8 V regulator), the external 1.8 V power supply must be energized before the 3.3 V supply. Otherwise, the 1.8 V supply may not lag the 3.3 V supply by more than 10 s. If a longer delay time is needed, the voltage difference between the two power supplies must be within 1.5 V during power supply ramp up. To avoid a potential latchup condition, voltage should be applied to input pins only after the device is powered-on as described above. LINEAR REGULATOR Although this device contains an on-board regulator, using its output to power external devices is not recommended. External loads can affect the regulator's stability and introduce noise into the supply. NXP cannot guarantee device performance at rated speeds and temperatures with external loads connected to this supply. CURRENT CONSUMPTION BY OPERATING MODE Current consumption can depend on a number of parameters. To make this data more usable, the values presented in Table 22 were derived under the conditions presented here. Maximum Specified Value The values specified in the MAXIMUM column were determined using these operating characteristics: * All IP blocks either operating or enabled at maximum frequency and size configuration * Core operating at maximum power configuration * All I/O loads at maximum (50 pF) * All voltages at maximum specified values * Maximum specified ambient temperature. Typical The values in the TYPICAL column were determined using a `typical' application under `typical' environmental conditions and the following operating characteristics: * SPI, Timer, and UART peripherals operating; all other peripherals disabled * LCD enabled with 320 x 240 x 16-bit color, 60 Hz refresh rate * I/O loads at nominal * FCLK = 51.6 MHz; HCLK = 51.6 MHz * All voltages at typical values * Nominal case temperature.
PERIPHERAL CURRENT CONSUMPTION In addition to the modal current consumption, Table 23 shows the typical current consumption for each of the on-board peripheral blocks. The values were determined with the peripheral clock running at maximum frequency, typical conditions, and no I/O loads. This current is supplied by the 1.8 V power supply. Table 22. Current Consumption by Mode
SYMBOL PARAMETER ACTIVE MODE ICHIP ICORE IIO Chip Current with Linear Regulator Core Current without Linear Regulator I/O Current without Linear Regulator 50.2 42.1 5 1.3 mA mA mA mA TYP. UNITS
IANALOG Analog Current
STANDBY MODE (TYPICAL CONDITIONS ONLY) ICHIP ICORE IIO Core Current with Linear Regulator Core Current without Linear Regulator Current drawn by I/O 42.7 34.6 0.8 1.3 mA mA mA mA
IANALOG Analog Current
SLEEP MODE (TYPICAL CONDITIONS ONLY) ICHIP ICORE IIO Core Current with Linear Regulator Core Current without Linear Regulator Current drawn by I/O 3.9 2.5 400 1.2 mA mA A mA
IANALOG Analog Current STOP1 MODE ISTOP Core Current with Linear Regulator, I/O, and 14.7456 MHz osc. STOP2 MODE (RTC ON) ILEAK Leakage Current, Core and I/O STOP2 MODE (RTC OFF) ILEAK Leakage Current, Core and I/O
2.96
mA
34
A
18
A
NOTES: 1. ICHIP = Chip Current with Linear Regulator (Core + I/O) 2. ICORE, IIO, IANALOG are the respective current consumption specifications for VDDC, VDD, and VDDA.
Table 23. Peripheral Current Consumption
PERIPHERAL UARTs RTC DMA SSP Counter/Timers LCD TYPICAL 200 5 4.1 500 200 2.2 UNITS A A mA A A mA
Preliminary data sheet
Rev. 01 -- 16 July 2007
39
LH75401/LH75411
NXP Semiconductors
System-on-Chip
AC Characteristics
All signal transitions are measured from the 50 % point of the signal. Table 24. Memory Interface Signals
SIGNAL D[15:0] D[15:0] D[15:0] nCS3 - nCS0 nCS3 -nCS0 nOE nOE I/O LOAD PARAMETER Out 50 pF Out 50 pF In Out 30 pF Out 30 pF Out 30 pF Out 30 pF tOVD tOHD tIDD tOVCS tOHCS tOVOE tOHOE tOVBE tOHBER tOHBEW tOVWE tOHWE tIVWAIT 3 x tHCLK - 6 ns 2 x tHCLK - 6 ns tHCLK + 10 ns 3 x tHCLK - 6 ns tHCLK + 10 ns 3 x tHCLK - 6 ns tHCLK + 10 ns 3 x tHCLK - 6 ns MINIMUM MAXIMUM tHCLK + 8 ns COMMENTS Data output valid following address valid Data output invalid following address valid 2 tHCLK - 18 ns Data input valid following address valid
2 x tHCLK - 18 ns Data Input Valid, following + (nWAIT -1) Address Valid (nWAIT states) x tHCLK
tHCLK + 6 ns
nCS output valid following address valid nCS output invalid following address valid nOE output valid following address valid nOE output invalid following address valid nBLE output valid following address valid nBLE output invalid following address valid, read cycle nBLE output invalid following address valid, write cycle nWE output valid following address valid
nBLE1 - nBLE0 Out 30 pF nBLE1 - nBLE0 Out 30 pF nBLE1 - nBLE0 Out 30 pF nWE nWE nWAIT Out 30 pF Out 30 pF In
2 x tHCLK - 6 ns 2 tHCLK - 2.2 ns nWE output invalid following address valid 2 tHCLK - 18 ns nWAIT input valid following address valid
NOTE: The values in Table 24 represent the timing with no internal arbitration delay and 1 wait state memory access. This is the worst case (fastest) timing.
Table 25. Synchronous Serial Port SIGNAL SSPFRM SSPTX SSPRX I/O Out Out In LOAD 50 pF 50 pF PARAMETER tOVSSPFRM tOVSSPTX tISSPRX 22 ns MIN. MAX. COMMENT
14 ns SSPFRM output valid, referenced to SSPCLK 12 ns SSPTX output valid, referenced to SSPCLK SSPRX input valid, referenced to SSPCLK
Table 26. Power-up Stabilization
PARAMETER tLREG tOSC32 tOSC14 tRSTOV tPORH DESCRIPTION Linear regulator stabilization time after power-up Oscillator stabilization time after Power Up (VDDC = VDDCMIN) Oscillator stabilization time after Power Up (VDDC = VDDCMIN) nPOR LOW to nPOR valid (once sampled LOW) nPOR hold extend to allow PLL to lock once XTAL is stable 3.5 10 TYP. MAX. 200 550 2.5 UNIT s ms ms HCLK s
40
Rev. 01 -- 16 July 2007
Preliminary data sheet
System-on-Chip
NXP Semiconductors
LH75401/LH75411
VDDmin
VDD
tOSC32
PLL
XTAL32
XTAL14 tOSC14 tPORH
LREG
VDDCmin tLREG
nPOR
LH754xx-100
Figure 7. Power-up Stabilization
MEMORY CONTROLLER WAVEFORMS Static Memory Controller Waveforms
Figure 8 shows the waveform and timing for an External Static Memory Write, with one Wait State. Figure 9 shows the waveform and timing for an External Static Memory Write, with two Wait States. Figure 10 shows the waveform and timing for an External Static Memory Read, with one Wait State. The SMC supports an nWAIT input that can be used by an external device to extend the wait time during a memory access. The SMC samples nWAIT at the beginning of at the beginning of each system clock cycle. The system clock cycle in which the nCSx signal is asserted counts as the first wait state. See Figure 11. The SMC recognizes that nWAIT is active within 2 clock cycles after it has been asserted. To assure that the current access (read or write) will be extended by nWAIT, program at least two wait states for this bank of
memory. If N wait states are programmed, the SMC holds this state for N system clocks or until the SMC detects that nWAIT is inactive, whichever occurs last. As the number of wait states programmed increases, the amount of delay before nWAIT must be asserted also increases. If only 2 wait states are programmed, nWAIT must be asserted in the clock cycle immediately following the clock cycle during which the nCSx signal is asserted. Once the SMC detects that the external device has deactivated nWAIT, the SMC completes its access in 3 system clock cycles. The formula for the allowable delay between asserting nCSx and asserting nWAIT is:
tASSERT = (system clock period) x (Wait States - 1) (where Wait States is from 2 to 31.)
The signal tIDD is shown without a setup time, as measurements are made from the Address Valid point and HCLK is an internal signal, shown for reference only.
Preliminary data sheet
Rev. 01 -- 16 July 2007
41
LH75401/LH75411
42
1 WAIT STATE ADDRESS tOHD tOVD DATA tOHCS tOVCS tOHWE tOVWE tOHBEW tOVBE
LH754xx-40
HCLK
(See Note 1)
A[23:0]
D[15:0]
NXP Semiconductors
nCSx
Figure 8. External Static Memory Write, One Wait State
Rev. 01 -- 16 July 2007
nWE
nWAIT
nBLE[1:0]
(See Note 2)
nOE
System-on-Chip
Preliminary data sheet
NOTES: 1. HCLK is an internal signal, provided for reference only. 2. The corresponding byte lane enable(s) become active.
2 WAIT STATES
System-on-Chip
HCLK (See Note 1) ADDRESS tOHD tOVD
Preliminary data sheet
DATA tOHCS tOVCS tOHWE tOVWE tOHBEW tOVBE
LH754xx-42
A[23:0]
D[15:0]
NXP Semiconductors
Figure 9. External Static Memory Write, Two Wait States
Rev. 01 -- 16 July 2007
nCSx
nWE
nWAIT
nBLE[1:0] (See Note 2)
nOE
LH75401/LH75411
NOTES: 1. HCLK is an internal signal, provided for reference only. 2. The corresponding byte lane enable(s) become active.
43
LH75401/LH75411
44
1 WAIT STATE ADDRESS tIDD DATA tOHCS tOVCS tOHBER tOVBE tOHOE tOVOE
HCLK
(See Note 1)
A[23:0]
D[15:0]
nCSx
NXP Semiconductors
Figure 10. External Static Memory Read, One Wait State
Rev. 01 -- 16 July 2007
nWE
nWAIT
nBLE[1:0]
(See Note 2)
nOE
DATA CAPTURED
System-on-Chip
Preliminary data sheet
NOTES: 1. HCLK is an internal signal, provided for reference only. 2. The corresponding byte lane enable(s) become active.
LH754xx-45
System-on-Chip
Preliminary data sheet
ADDRESS DATA tIVWAIT DATA CAPTURED
LH754xx-47
HCLK
(See Note 1)
A[23:0]
D[15:0]
nCSx
NXP Semiconductors
Figure 11. External Static Memory Read, nWAIT Active
Rev. 01 -- 16 July 2007
nWE
nWAIT
nBLE[1:0]
(See Note 2)
nOE
LH75401/LH75411
NOTES: 1. HCLK is an internal signal, provided for reference only. 2. The corresponding byte lane enable(s) become active.
45
LH75401/LH75411
NXP Semiconductors
System-on-Chip
Synchronous Serial Port Waveform
754xx-49
tOVSSPFRM
tOVSSPTX
SSPCLK
SSPTX
tISSPRX
Figure 12. Synchronous Serial Port Waveform
46
Rev. 01 -- 16 July 2007
SSPFRM
SSPRX
Preliminary data sheet
System-on-Chip
NXP Semiconductors
LH75401/LH75411
DMA Controller Timing Diagrams
Figure 13 and Figure 14 show examples of DMA timing diagrams.
* Figure 13 shows the timing for a peripheral-to-memory data transfer, where
SoSize = DeSize and SoBurst = 4. * Figure 14 shows the timing for a memory-to-peripheral data transfer, where SoSize = DeSize and SoBurst = 4.
Ma3
Ma2
Ma1
Ma0
Pa3
Pa2
Pa1
Pa0
Pd0
Pd1
Pd2
Pd3
Md0
Md1
Md2
Md3
DREQ
A[23:0]
D[15:0]
nCS0
Figure 13. Peripheral-to-Memory Data-Transfer Timing
Preliminary data sheet
DACK
Rev. 01 -- 16 July 2007
nCS1
nWE
LH754xx-10
47
LH75401/LH75411
NXP Semiconductors
System-on-Chip
Pa3
Pa2
Pa1
Pa0
Ma3
Ma2
Ma1
DREQ
A[23:0]
Ma0
D[15:0]
Md0
Md1
Md2
Md3
Pd0
Pd1
Pd2
Pd3
nCS0
nCS1
Figure 14. Memory-to-Peripheral Data-Transfer Timing
48
DACK
Rev. 01 -- 16 July 2007
nWE
Preliminary data sheet
LH754xx-11
System-on-Chip
NXP Semiconductors
LH75401/LH75411
Color LCD Controller Timing Waveforms
This section describes typical output waveform diagrams for the CLCDC and the Advanced LCD Interface. STN HORIZONTAL TIMING Figure 15 shows typical horizontal timing waveforms for STN panels. In this figure, the CLCDC Clock (an input to the CLCDC) is scaled within the CLCDC and used to produce the LCDDCLK output. Programmable registers in the CLCDC set the timings (in terms of LCDDCLK pulses) to produce the other signals that control an STN display.
TFT HORIZONTAL TIMING Figure 17 shows typical horizontal timing waveforms for TFT panels. TFT VERTICAL TIMING Figure 18 shows typical vertical timing waveforms for TFT panels. AD-TFT/HR-TFT HORIZONTAL TIMING WAVEFORMS Figure 19 shows typical horizontal timing waveforms for AD-TFT and HR-TFT panels. The ALI adjusts the normal TFT timing to accommodate these panels. AD-TFT/HR-TFT VERTICAL TIMING WAVEFORMS Figure 20 shows typical vertical timing waveforms for AD-TFT and HR-TFT panels. The power sequencing and register information is the same as for TFT vertical timing.
For example, Figure 15 shows that the duration of the LCDLP signal is controlled by Timing0:HSW (the HSW bit field in the Timing0 Register). Figure 15 also shows that the polarity of the LCDLP signal is set by Timing2:IHS.
STN VERTICAL TIMING Figure 16 shows typical vertical timing waveforms for STN panels.
Preliminary data sheet
Rev. 01 -- 16 July 2007
49
LH75401/LH75411
50
1 STN HORIZONTAL LINE TIMING0:HSW LCDDCLK IS SUPPRESSED DURING LCDLP TIMING0:HBP 16 x (TIMING0:PPL+1) TIMING0:HFP HORIZONTAL BACK PORCH ENUMERATED IN 'LCDDCLKS' D001 D002 D.... DNNN HORIZONTAL FRONT PORCH ONE 'LINE' OF LCD DATA ENUMERATED IN 'LCDDCLKS'
LH754xx-77
CLCDC CLOCK (INTERNAL) APBPERIPHCLKCTRL1:LCD CLKPRESCALE:LCDPS
LCDLP (LINE SYNCHRONIZATION PULSE) TIMING2:IHS
NXP Semiconductors
Figure 15. STN Horizontal Timing Diagram
Rev. 01 -- 16 July 2007
LCDDCLK (PANEL CLOCK) TIMING2:PCD TIMING2:BCD TIMING2:IPC TIMING2:CPL
LCDVD[11:0] (PANEL DATA) THE ACTIVE DATA LINES WILL VARY WITH THE TYPE OF STN PANEL: 4-BIT, 8-BIT, COLOR, OR MONO
System-on-Chip
Preliminary data sheet
NOTES: 1. The CLCDC clock (from the RCPC) is scaled within the CLCDC and used to produce the LCDDCLK output. CLCDC registers set timing (in terms of LCDDCLK pulses) to produce the other signals that control an STN display. 2. The duration ot the LCDLP signal is controlled by TIMING0:HSW (the HSW bit field in the TIMING0 Register). 3. The polarity of the LCDLP signal is set by TIMING2:IHS.
System-on-Chip
Preliminary data sheet
DISPLAY-DEPENDENT TURN-ON DELAY 1 STN FRAME DISPLAY DEPENDENT TURN-OFF DELAY PANEL POSITIVE HIGH-VOLTAGE SUPPLY ACTIVE PANEL NEGATIVE HIGH-VOLTAGE SUPPLY ACTIVE PANEL LOGIC ACTIVE PANEL DATA CLOCK ACTIVE DATA ENABLE Timing1: VSW Timing1: VBP Timing1: LPP Timing1: VFP BACK PORCH ENUMERATED IN HORIZONTAL 'LINES' ALL 'LINES' FOR ONE FRAME FRONT PORCH ENUMERATED IN HORIZONTAL 'LINES' SEE 'STN HORIZONTAL TIMING DIAGRAM'
LH754xx-82
VDD
VSS
See Note 2
LCDVDDEN (DIGITAL SUPPLY ENABLE FOR HIGH-VOLTAGE SUPPLIES)
LCDDCLK (PANEL CLOCK) Timing2:PCD Timing2: BCD Timing2: IPC Timing2: CPL
NXP Semiconductors
Figure 16. STN Vertical Timing Diagram
Rev. 01 -- 16 July 2007
LCDEN (DATA ENABLE) Timing2:ACB Timing2: IOE
LCDFP (VERTICAL SYNCHRONIZATION PULSE) Timing1: IVS (See Note 3)
PIXEL DATA AND HORIZONTAL CONTROL SIGNALS FOR ONE FRAME
LH75401/LH75411
NOTES: 1. Signal polarties may vary for some displays. 2. See 'STN horizontal timing' diagram. 3. LCDFP with Timing1:VSW = 0 is only a single horizontal ine period.
51
LH75401/LH75411
52
1 TFT HORIZONTAL LINE Timing0:HSW Timing0:HBP Timing0:PPL Timing0:HFP HORIZONTAL BACK PORCH ENUMERATED IN 'LCDDCLKS' D001 D002 D.... DNNN HORIZONTAL FRONT PORCH ONE 'LINE' OF LCD DATA ENUMERATED IN 'LCDDCLKS'
LH754xx-79
CLCDC CLOCK (INTERNAL) APBPeriphClkCtrl1:LCD ClkPrescale:LCDPS
LCDLP (HORIZONTAL SYNCHRONIZATION PULSE) LCDTiming2:IHS
NXP Semiconductors
Figure 17. TFT Horizontal Timing Diagram
Rev. 01 -- 16 July 2007
LCDDCLK (PANEL CLOCK) TIMING2:PCD TIMING2:BCD TIMING2:IPC TIMING2:CPL
LCDVD[11:0] (PANEL DATA)
System-on-Chip
Preliminary data sheet
NOTES: 1. The CLCDC clock (from the RCPC) is scaled within the CLCDC and used to produce the LCDDCLK output. CLCDC registers set timing (in terms of LCDDCLK pulses) to produce the other signals that control a TFT display. 2. The duration ot the LCDLP signal is controlled by Timing0:HSW (the HSW bit field in the Timing0 Register). 3. The polarity of the LCDLP signal is set by Timing2:IHS.
System-on-Chip
Preliminary data sheet
DISPLAY-DEPENDENT TURN-ON DELAY 1 TFT FRAME DISPLAY DEPENDENT TURN-OFF DELAY PANEL POSITIVE HIGH-VOLTAGE SUPPLY ACTIVE PANEL NEGATIVE HIGH-VOLTAGE SUPPLY ACTIVE PANEL LOGIC ACTIVE PANEL DATA CLOCK ACTIVE DATA ENABLE Timing1: VSW Timing1: VBP Timing1: LPP Timing1: VFP BACK PORCH ENUMERATED IN HORIZONTAL 'LINES' ALL 'LINES' FOR ONE FRAME FRONT PORCH ENUMERATED IN HORIZONTAL 'LINES' SEE 'TFT HORIZONTAL TIMING DIAGRAM'
LH754xx-78
VDD
See Note 2
VSS
LCDVDDEN (DIGITAL SUPPLY ENABLE)
LCDDCLK (PANEL CLOCK) Timing2:PCD Timing2: BCD Timing2: IPC
NXP Semiconductors
Figure 18. TFT Vertical Timing Diagram
Rev. 01 -- 16 July 2007
LCDEN (DATA ENABLE) Timing2:ACB Timing2: IOE
LCDFP (VERTICAL SYNCHRONIZATION PULSE) Timing1: IVS
PIXEL DATA AND HORIZONTAL CONTROL SIGNALS FOR ONE FRAME
LH75401/LH75411
NOTES: 1. Signal polarties may vary for some displays. 2. The use of LCDDSPLEN for high-voltage power control is optional on some TFT panels.
53
LH75401/LH75411
NXP Semiconductors
System-on-Chip
1 AD-TFT or HR-TFT HORIZONTAL LINE
*
CLCDCLK (INTERNAL) APBPeriphClkCtrl1:LCD ClkPrescale:LCDPS (SHOWN FOR REFERENCE) LCDLP (HORIZONTAL SYNCHRONIZATION PULSE) LCDDCLK (PANEL CLOCK) Timing2:PCD Timing2:BCD Timing2:IPC Timing2:CPL
AD-TFT and HR-TFT SIGNALS ARE TFT SIGNALS, RE-TIMED Timing0:HSW
INPUTS TO THE ALI FROM THE CLCDC
LCDVD[11:0]
001 002 003 004 005 006 007 008 PIXEL DATA Timing0:HSW + Timing0: HBP
320
LCDEN (DATA ENABLE) LCDDCLK (DELAYED FOR AD-TFT, HR-TFT) LCDVD[11:0] (DELAYED FOR AD-TFT, HR-TFT) 001 002 003 004 005 006 317 318 319 320
OUTPUTS FROM THE ALI TO THE PANEL
LCDSPL (AD-TFT, HR-TFT START PULSE LEFT) Timing1:LPDEL LCDLP (HORIZONTAL SYNCHRONIZATION PULSE)
1 LCDDCLK
1 LCDDCLK
Timing1:CLSDEL
Timing2:CLSDEL2
LCDCLS
LCDPS Timing1:REVDEL
LCDREV
NOTE: * Source is RCPC.
LH754xx-80
Figure 19. AD-TFT, HR-TFT Horizontal Timing Diagram
Timing1:VSW LCDSPS (VERTICAL SYNCHRONIZATION) LCDLP (HORIZONTAL SYNCHRONIZATION PULSE) LCDVD[11:0] (LCD VIDEO DATA)
1.5 s - 4 s
NOTE: LCDDCLK can range from 4.5 MHz to 6.8 MHz.
LH754xx-81
Figure 20. AD-TFT, HR-TFT Vertical Timing Diagram
54
Rev. 01 -- 16 July 2007
Preliminary data sheet
System-on-Chip
NXP Semiconductors
LH75401/LH75411
SUGGESTED EXTERNAL COMPONENTS
Figure 21 shows the suggested external components for the 32.768 kHz crystal circuit to be used with the NXP LH75401/LH75411. The NAND gate represents the logic inside the SoC. See the chart for crystal specifics.
Figure 22 shows the suggested external components for the 14.7456 MHz crystal circuit to be used with the NXP LH75401/LH75411. The NAND gate represents the logic inside the SoC. See the chart for crystal specifics.
INTERNAL TO THE LH75400, LH75401, LH75410, LH75411 EXTERNAL TO THE LH75400, LH75401, LH75410, LH75411
ENABLE
XTAL32IN
Y1
XTAL32OUT
32.768 kHz R1 18 M C1 15 pF GND NOTES: 1. Y1 is a parallel-resonant type crystal. (See table) 2. The nominal values for C1 and C2 shown are for a crystal specified at 12.5 pF load capacitance (CL). 3. The values for C1 and C2 are dependent upon the cystal's specified load capacitance and PCB stray capacitance. 4. R1 must be in the circuit. 5. Ground connections should be short and return to the ground plane which is connected to the processor's core ground pins. 6. Tolerance for R1, C1, C2 is 5%. C2 18 pF GND
RECOMMENDED CRYSTAL SPECIFICATIONS PARAMETER 32.768 kHz Crystal Tolerance Aging Load Capacitance ESR (MAX.) Drive Level Recommended Part DESCRIPTION Parallel Mode 30 ppm 3 ppm 12.5 pF 50 k 1.0 W (MAX.) MTRON SX1555 or equivalent
LH754xx-101
Figure 21. Suggested External Components, 32.768 kHz Oscillator
Preliminary data sheet
Rev. 01 -- 16 July 2007
55
LH75401/LH75411
NXP Semiconductors
System-on-Chip
INTERNAL TO THE LH75400, LH75401, LH75410, LH75411 EXTERNAL TO THE LH75400, LH75401, LH75410, LH75411
ENABLE
XTALIN
Y1
XTALOUT
14.7456 MHz R1 1 M C1 18 pF GND C2 22 pF GND
RECOMMENDED CRYSTAL SPECIFICATIONS NOTES: 1. Y1 is a parallel-resonant type crystal. (See table) 2. The nominal values for C1 and C2 shown are for a crystal specified at 18 pF load capacitance (CL). 3. The values for C1 and C2 are dependent upon the cystal's specified load capacitance and PCB stray capacitance. 4. R1 must be in the circuit. 5. Ground connections should be short and return to the ground plane which is connected to the processor's core ground pins. 6. Tolerance for R1, C1, C2 is 5%. PARAMETER 14.7456 MHz Crystal Tolerance Stability Aging Load Capacitance ESR (MAX.) Drive Level Recommended Part DESCRIPTION (AT-Cut) Parallel Mode 50 ppm 100 ppm 5 ppm 18 pF 40 100 W (MAX.) MTRON SX2050 or equivalent
LH754xx-102
Figure 22. Suggested External Components, 14.7456 MHz Oscillator
56
Rev. 01 -- 16 July 2007
Preliminary data sheet
System-on-Chip
NXP Semiconductors
LH75401/LH75411
PACKAGE SPECIFICATIONS
LQFP144: plastic low profile quad flat package; 144 leads; body 20 x 20 x 1.4 mm SOT486-1
c
y X
A 108 109 73 72 ZE
e
E HE
A A2
A1
(A 3) Lp L detail X
wM bp pin 1 index 144 1 wM D HD ZD B vM B 36 bp vM A 37
e
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.6 A1 0.15 0.05 A2 1.45 1.35 A3 0.25 bp 0.27 0.17 c 0.20 0.09 D (1) 20.1 19.9 E (1) 20.1 19.9 e 0.5 HD HE L 1 Lp 0.75 0.45 v 0.2 w 0.08 y 0.08 Z D(1) Z E(1) 1.4 1.1 1.4 1.1 7 o 0
o
22.15 22.15 21.85 21.85
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT486-1 REFERENCES IEC 136E23 JEDEC MS-026 JEITA EUROPEAN PROJECTION
ISSUE DATE 00-03-14 03-02-20
Figure 23. Package outline SOT486-1 (LQFP144)
Preliminary data sheet
Rev. 01 -- 16 July 2007
57
LH75401/LH75411
NXP Semiconductors
System-on-Chip
144LQFP
21.2 0.5 1.6 0.3 17.5 17.5 NOTE: Dimensions in mm.
144LQFP
Figure 24. Recommended PCB Footprint
58
Rev. 01 -- 16 July 2007
19.6
22.8
Preliminary data sheet
System-on-Chip
NXP Semiconductors
LH75401/LH75411
REVISION HISTORY
Table 27. Revision history
Document ID LH75401_411_N_1 Modifications: Release date 20070716 Data sheet status Preliminary data sheet Change notice Supersedes LH754xx Data Sheet 5-10-07
* First NXP version based on the LH75400/01/10/11 data sheet of 20070510
Preliminary data sheet
Rev. 01 -- 16 July 2007
59
LH75401/LH75411
NXP Semiconductors
System-on-Chip
1. Legal information
1.1 Data sheet status
Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
1.2
Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
malfunction of a NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.
1.3
Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or
1.4
Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.
2. Contact information
For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: salesaddresses@nxp.com
(c) NXP B.V. 2007. All rights reserved.
IMPORTANT NOTICE
Dear customer, As from June 1st, 2007 NXP Semiconductors has acquired the LH7xxx ARM Microcontrollers from Sharp Microelectronics. The following changes are applicable to the attached data sheet. In data sheets where the previous Sharp or Sharp Corporation references remain, please use the new links as shown below. For www.sharpsma.com use www.nxp.com/microcontrollers for indicated sales addresses use salesaddresses@nxp.com (email) The copyright notice at the bottom of each page (or elsewhere in the document, depending on the version) - Copyright (c) (year) by SHARP Corporation. is replaced with: - (c) NXP B.V. (year). All rights reserved. If you have any questions related to the data sheet, please contact our nearest sales office via e-mail or phone (details via salesaddresses@nxp.com). Thank you for your cooperation and understanding, In addition to that the Annex A (attached hereto) is added to the document.
NXP Semiconductors
ANNEX A: Disclaimers (11)
1. t001dis100.fm: General (DS, AN, UM) General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. 2. t001dis101.fm: Right to make changes (DS, AN, UM) Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. 3. t001dis102.fm: Suitability for use (DS, AN, UM) Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of a NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. 4. t001dis103.fm: Applications (DS, AN, UM) Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 5. t001dis104.fm: Limiting values (DS) Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. 6. t001dis105.fm: Terms and conditions of sale (DS) Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail.
7. t001dis106.fm: No offer to sell or license (DS) No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 8. t001dis107.fm: Hazardous voltage (DS, AN, UM; if applicable) Hazardous voltage -- Although basic supply voltages of the product may be much lower, circuit voltages up to 60 V may appear when operating this product, depending on settings and application. Customers incorporating or otherwise using these products in applications where such high voltages may appear during operation, assembly, test etc. of such application, do so at their own risk. Customers agree to fully indemnify NXP Semiconductors for any damages resulting from or in connection with such high voltages. Furthermore, customers are drawn to safety standards (IEC 950, EN 60 950, CENELEC, ISO, etc.) and other (legal) requirements applying to such high voltages. 9. t001dis108.2.fm: Bare die (DS; if applicable) Bare die (if applicable) -- Products indicated as Bare Die are subject to separate specifications and are not tested in accordance with standard testing procedures. Product warranties and guarantees as stated in this document are not applicable to Bare Die Products unless such warranties and guarantees are explicitly stated in a valid separate agreement entered into by NXP Semiconductors and customer. 10. t001dis109.fm: AEC unqualified products (DS, AN, UM; if applicable) AEC unqualified products -- This product has not been qualified to the appropriate Automotive Electronics Council (AEC) standard Q100 or Q101 and should not be used in automotive critical applications, including but not limited to applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is for the customer's own risk. 11. t001dis110.fm: Suitability for use in automotive applications only (DS, AN, UM; if applicable) Suitability for use in automotive applications only -- This NXP Semiconductors product has been developed for use in automotive applications only. The product is not designed, authorized or warranted to be suitable for any other use, including medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk.

▲Up To Search▲

Price & Availability of LH75401N0Q100C0

	To Download LH75401N0Q100C0 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .